Logic selection guide 2016

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Buffers-inverters-drivers (cont.) Type number Description V CC (V) Logic switching levels Output drive capability (mA) Output Load C L (Typ) 74AUP1G240 Single inverter/line driver (3-state) 1.1 to 3.6 CMOS ±1.9 30 pF 4.2 70 -40 to +125 74AUP1G34 Single buffer 1.1 to 3.6 CMOS ±1.9 30 pF 3.9 70 -40 to +125 74AUP1GU04 Single inverter; unbuffered 1.1 to 3.6 CMOS ±1.9 30 pF 2.3 70 -40 to +125 74AUP2G04 Dual inverter 1.1 to 3.6 CMOS ±1.9 30 pF 4 70 -40 to +125 74AUP2G06 Dual inverter; open drain 1.1 to 3.6 CMOS 1,9 30 pF 4.5 70 -40 to +125 74AUP2G07 Dual buffer; open drain 1.1 to 3.6 CMOS 1,9 30 pF 4.4 70 -40 to +125 74AUP2G125 Dual buffer/line driver (3-state) 1.1 to 3.6 CMOS ±1.9 30 pF 4.3 70 -40 to +125 74AUP2G126 Dual buffer/line driver (3-state) 1.1 to 3.6 CMOS ±1.9 30 pF 4.3 70 -40 to +125 74AUP2G14 Dual inverter; Schmitt trigger 1.1 to 3.6 CMOS ±1.9 30 pF 4.7 70 -40 to +125 74AUP2G240 Dual inverter/line driver (3-state) 1.1 to 3.6 CMOS ±1.9 30 pF 4.2 70 -40 to +125 74AUP2G241 Dual buffer/line driver (3-state) 1.1 to 3.6 CMOS ±1.9 30 pF 4.3 70 -40 to +125 74AUP2G34 Dual buffer 1.1 to 3.6 CMOS ±1.9 30 pF 3.9 70 -40 to +125 74AUP2GU04 Dual inverter; unbuffered 1.1 to 3.6 CMOS ±1.9 30 pF 2.3 70 -40 to +125 74AUP3G04 Triple inverter 1.1 to 3.6 CMOS ±1.9 30 pF 4 70 -40 to +125 74AVC16244 16-bit buffer/line driver (3-state) 0.8 to 3.6 74AVCH16244 16-bit buffer/line driver with bus hold (3-state) 0.8 to 3.6 CMOS/ LVTTL CMOS/ LVTTL t pd (ns) f max (MHz) T amb (°C) ±12 30 pF 2 200 -40 to +85 ±12 30 pF 2 200 -40 to +85 74AXP1G06 Single inverter; open drain 0.7 to 2.75 CMOS 4,5 5pF 3.5 70 -40 to +85 74AXP1G125 Single buffer/line driver (3-state) 0.7 to 2.75 CMOS ±4.5 5pF 2.7 70 -40 to +85 74HC04 Hex inverter 2.0 to 6.0 CMOS ±5.2 50 pF 7 36 -40 to +125 74HCT04 Hex inverter; TTL-enabled 4.5 to 5.5 TTL ±4.0 50 pF 8 36 -40 to +125 74HC125 Quad buffer/line driver (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 9 36 -40 to +125 74HCT125 Quad buffer/line driver (3-state) 4.5 to 5.5 TTL ±6 50 pF 12 36 -40 to +125 74HC126 Quad buffer/line driver (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 9 36 -40 to +125 74HCT126 Quad buffer/line driver (3-state) 4.5 to 5.5 TTL ±6 50 pF 11 36 -40 to +125 74HC1G04 Single inverter 2.0 to 6.0 CMOS ±2.6 50 pF 7 36 -40 to +125 74HCT1G04 Single inverter; TTL-enabled 4.5 to 5.5 TTL ±2.0 50 pF 8 36 -40 to +125 74HC1G125 Single buffer/line driver (3-state) 2.0 to 6.0 CMOS ±2.6 50 pF 9 36 -40 to +125 74HCT1G125 Single buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±2.0 50 pF 10 36 -40 to +125 74HC1G126 Single buffer/line driver (3-state) 2.0 to 6.0 CMOS ±2.6 50 pF 9 36 -40 to +125 74HCT1G126 Single buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±2.0 50 pF 10 36 -40 to +125 74HC240 Octal inverter/line driver (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 9 36 -40 to +125 74HCT240 Octal inverter/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 9 36 -40 to +125 74HCT240 Octal inverter/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 9 36 -40 to +125 74HCT240 Octal inverter/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 9 36 -40 to +125 74HC241 Octal buffer/line driver (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 7 36 -40 to +125 74HCT241 Octal buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 11 36 -40 to +125 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. 70 NXP Logic selection guide 2016
Buffers-inverters-drivers (cont.) Type number Description V CC (V) Logic switching levels Output drive capability (mA) Output Load C L (Typ) 74HC244 Octal buffer/line driver (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 9 36 -40 to +125 74HCT244 Octal buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 11 36 -40 to +125 74HC2G04 Dual inverter 2.0 to 6.0 CMOS ±5.2 50 pF 8 36 -40 to +125 74HCT2G04 Dual inverter; TTL-enabled 4.5 to 5.5 TTL ±4.0 50 pF 10 36 -40 to +125 74HC2G125 Dual buffer/line driver (3-state) 2.0 to 6.0 CMOS ±5.2 50 pF 10 36 -40 to +125 74HCT2G125 Dual buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±4.0 50 pF 12 36 -40 to +125 74HC2G126 Dual buffer/line driver (3-state) 2.0 to 6.0 CMOS ±5.2 50 pF 10 36 -40 to +125 74HC2G34 Dual buffer 2.0 to 6.0 CMOS ±5.2 50 pF 9 36 -40 to +125 74HCT2G34 Dual buffer; TTL-enabled 4.5 to 5.5 TTL ±4 50 pF 10 32 -40 to +125 74HC365 Hex buffer/line driver (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 9 36 -40 to +125 74HCT365 Hex buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 11 36 -40 to +125 74HC366 Hex inverter/line driver (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 10 36 -40 to +125 74HCT366 Hex inverter/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 11 36 -40 to +125 74HC367 Hex buffer/line driver (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 8 36 -40 to +125 74HCT367 Hex buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 11 36 -40 to +125 74HC368 Hex inverter/line driver (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 9 36 -40 to +125 74HCT368 Hex inverter/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 11 36 -40 to +125 74HC3G04 Triple inverter 2.0 to 6.0 CMOS ±5.2 50 pF 8 36 -40 to +125 74HCT3G04 Triple inverter; TTL-enabled 4.5 to 5.5 TTL ±4.0 50 pF 10 36 -40 to +125 74HC3G06 Triple inverter; open drain 2.0 to 6.0 CMOS 5,2 50 pF 9 36 -40 to +125 74HCT3G06 Triple inverter; open drain; TTL-enabled 4.5 to 5.5 TTL 4 50 pF 9 36 -40 to +125 74HC3G07 Triple buffer; open drain 2.0 to 6.0 CMOS 5,2 50 pF 9 36 -40 to +125 74HCT3G07 Triple buffer; open drain; TTL-enabled 4.5 to 5.5 TTL 4 50 pF 9 36 -40 to +125 74HC3G34 Triple buffer 2.0 to 6.0 CMOS ±5.2 50 pF 9 36 -40 to +125 74HCT3G34 Triple buffer; TTL-enabled 4.5 to 5.5 TTL ±4.0 50 pF 10 36 -40 to +125 74HC540 Octal inverter/line driver (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 9 36 -40 to +125 74HCT540 Octal inverter/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 11 36 -40 to +125 74HC541 Octal buffer/line driver (3-state) 2.0 to 6.0 CMOS ±7.8 50 pF 10 36 -40 to +125 74HCT541 Octal buffer/line driver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 50 pF 12 36 -40 to +125 74HC05 Hex inverter; open drain 2.0 to 6.0 CMOS 5,2 50 pF 11 36 -40 to +125 74HC1GU04 Single inverter; unbuffered 2.0 to 6.0 CMOS ±2.6 50 pF 5 36 -40 to +125 74HC2GU04 Single inverter; unbuffered 2.0 to 6.0 CMOS ±2.6 50 pF 5 36 -40 to +125 74HC3GU04 Triple inverter; unbuffered 2.0 to 6.0 CMOS ±5.2 50 pF 6 36 -40 to +125 74HC3GU04 Triple inverter; unbuffered 2.0 to 6.0 CMOS ±5.2 50 pF 6 36 -40 to +125 74HCU04 Hex inverter; unbuffered 2.0 to 6.0 CMOS ±5.2 50 pF 5 36 -40 to +125 74LV04 Hex inverter 1.0 to 5.5 CMOS ±12 50 pF 6 30 -40 to +125 74LV125 Quad buffer/line driver (3-state) 1.0 to 5.5 CMOS ±16 50 pF 9 30 -40 to +125 t pd (ns) f max (MHz) T amb (°C) Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. NXP Logic selection guide 2016 71
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Logic selection guide 2016 Standard
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Standard Logic and Mini Logic: tune
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Transceivers 120 Standard logic pac
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NXP is the #1 volume leader For the
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What is configurable logic? Configu
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Our approach to quality At NXP, we
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Low-voltage families INCREASING PER
Page 15 and 16:
Special features NXP offers a varie
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SOURCE TERMINATION What it does Imp
Page 19 and 20: OVERVOLTAGE-TOLERANT OUTPUTS 3-stat
Page 21 and 22: LIVE INSERTION What it does Enables
Page 23 and 24: OPEN-DRAIN OUTPUTS Open-drain outpu
Page 25 and 26: High-voltage families This section
Page 27 and 28: HEF4000B selection table (cont.) SO
Page 29 and 30: HC(T) selection table (cont.) TSSOP
Page 39 and 40: AHC(T) selection table (cont.) TSSO
Page 41 and 42: AHC(T) selection table (cont.) TSSO
Page 43 and 44: XC7 LOGIC XC7 devices are very high
Page 45 and 46: CBT(D) LOGIC CBT and CBTD bus switc
Page 47 and 48: LV selection table TSSOP SSOP SO DQ
Page 49 and 50: LVC selection table (cont.) TSSOP V
Page 55 and 56: ALVC selection table (cont.) TSSOP
Page 57 and 58: LVT selection table (cont.) TSSOP S
Page 59 and 60: AVC(M) LOGIC AVC and AVCM devices a
Page 61 and 62: AUP selection table (cont.) VSSOP M
Page 63 and 64: AXP LOGIC As the first logic family
Page 65 and 66: Product listing by function Analog
Page 67 and 68: Analog switches (cont.) Type number
Page 69: Buffers-inverters-drivers (cont.) T
Page 73 and 74: Buffers-inverters-drivers (cont.) T
Page 75 and 76: BUS SWITCHES Features and benefits
Page 77 and 78: Counters/frequency dividers (cont.)
Page 79 and 80: Decoders demultiplexers (cont.) Typ
Page 81 and 82: Digital multiplexers (cont.) Type n
Page 83 and 84: Flip-flops (cont.) Type number Desc
Page 85 and 86: Flip-flops (cont.) Type number Desc
Page 87 and 88: GATES This section includes AND gat
Page 89 and 90: Gates - Configurable Type number De
Page 91 and 92: Gates - NAND (cont.) Type number De
Page 93 and 94: Gates - OR (cont.) Type number Desc
Page 95 and 96: Latches-registered drivers (cont.)
Page 97 and 98: Level shifters-translators (cont.)
Page 99 and 100: PARITY GENERATORS/CHECKERS Features
Page 101 and 102: Schmitt triggers (cont.) Type numbe
Page 103 and 104: Shift registers - LED drivers (cont
Page 105 and 106: Transceivers (cont.) Type number De
Page 107 and 108: Q100 Standard Logic functions & pac
Page 109 and 110: Buffers/inverters (cont.) Features
Page 111 and 112: Counters/frequency dividers (cont.)
Page 113 and 114: Flip-flops (cont.) Features Package
Page 115 and 116: Gates (cont.) Features Package (suf
Page 117 and 118: Level shifters/translators Features
Page 119 and 120: Shift registers (cont.) Features Pa
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Standard logic packages Package suf
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Buffers/inverters (cont.) Features
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Digital decoders/demultiplexers Fea
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Gates (cont.) Features Package (suf
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Level shifters/translators Features
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The leadless advantage Today’s ul
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Nomenclature NXP's naming conventio
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SOT457 GV SOT505-2 DP Pinout Pinout
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SOT765-1 DC SOT833-1 GT Pinout Pino
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SOT902-2 GM SOT996 GD Pinout Pinout
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SOT1089 GF SOT1202 GS Pinout Pinout
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SOT815-1 BQ SOT402-1 PW Pinout Pino
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SOT337-1 DB SOT338-1 DB Pinout Pino
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SOT724-1 DS SOT1174 GM Pinout Pinou
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SOT556-1 DK SOT340-1 DB Pinout Pino
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Design tools NXP is committed to ma
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Evaluation board for configurable l
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Toshiba one gate IDT logic TC7 S Z
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