Logic selection guide 2016

Recommendations

Info

SOT650-1 TK SOT753-1 GV Pinout Pinout 10 6 5 4 1 2 3 1 5 Package dimensions Transparent top view Package dimensions 3.1 2.9 3.1 2.7 1.1 0.9 0.5 1 2.0 5 0.30 0.18 1.0 0.05 0.00 5 4 0.6 0.2 0.55 0.30 3.1 2.9 10 2.55 2.15 Dimensions in mm 6 1.75 1.45 14-10-01 3.0 2.5 1.7 1.3 1 2 3 0.40 0.95 0.25 1.9 Dimensions in mm 0.26 0.10 14-10-03 Footprint information for reflow soldering of HVSON10 package Solder footprint SOT650-1 Solder footprint Gx D P (0.105) C nSPx SPx SPy Hy Gy SPy tot nSPy SLy By Ay SPx tot SLx Generic footprint pattern Refer to the package outline drawing for actual layout solder land solder paste deposit solder land plus solder paste occupied area DIMENSIONS in mm P Ay By C D SLx SLy SPx tot SPy tot SPx SPy Gx Gy Hy nSPx nSPy 4.000 2.200 0.500 0.240 0.900 2.400 1.500 1.400 0.650 0.550 0.650 3.300 3.300 4.250 2 1 Issue date 09-12-29 09-12-29 sot650-1_fr 136 NXP Logic selection guide 2016
SOT765-1 DC SOT833-1 GT Pinout Pinout 8 5 8 7 6 5 1 4 1 2 3 4 Transparent top view Package dimensions Package dimensions 2.1 1.9 8 5 1.0 max 0.15 0.00 1 2 2.0 1.9 3 4 0.25 0.17 0.5 0.04 3.2 3.0 2.4 2.2 0.40 0.15 1.05 0.95 0.6 0.40 0.32 0.35 0.27 1 4 0.27 Footprint information for reflow soldering 0.5 of VSSOP8 package 0.17 Dimensions in mm 0.23 0.08 14-10-01 8 SOT765-1 Dimensions in mm 7 6 0.5 0.5 0.5 5 14-09-30 Solder footprint Solder footprint Hx Gx P2 D1 (0.125) Hy Gy By Ay C (0.175) (0.125) D2 (4x) P1 Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 Ay By C D1 D2 Gx Gy Hx Hy 0.500 0.550 3.500 2.000 0.750 0.300 0.400 2.250 1.750 3.075 3.750 sot765-1_fr NXP Logic selection guide 2016 137
Page 1 and 2:
Logic selection guide 2016 Standard
Page 3 and 4:
Standard Logic and Mini Logic: tune
Page 5 and 6:
Transceivers 120 Standard logic pac
Page 7 and 8:
NXP is the #1 volume leader For the
Page 9 and 10:
What is configurable logic? Configu
Page 11 and 12:
Our approach to quality At NXP, we
Page 13 and 14:
Low-voltage families INCREASING PER
Page 15 and 16:
Special features NXP offers a varie
Page 17 and 18:
SOURCE TERMINATION What it does Imp
Page 19 and 20:
OVERVOLTAGE-TOLERANT OUTPUTS 3-stat
Page 21 and 22:
LIVE INSERTION What it does Enables
Page 23 and 24:
OPEN-DRAIN OUTPUTS Open-drain outpu
Page 25 and 26:
High-voltage families This section
Page 27 and 28:
HEF4000B selection table (cont.) SO
Page 29 and 30:
HC(T) selection table (cont.) TSSOP
Page 31 and 32:
Page 33 and 34:
Page 35 and 36:
Page 37 and 38:
Page 39 and 40:
AHC(T) selection table (cont.) TSSO
Page 41 and 42:
AHC(T) selection table (cont.) TSSO
Page 43 and 44:
XC7 LOGIC XC7 devices are very high
Page 45 and 46:
CBT(D) LOGIC CBT and CBTD bus switc
Page 47 and 48:
LV selection table TSSOP SSOP SO DQ
Page 49 and 50:
LVC selection table (cont.) TSSOP V
Page 51 and 52:
Page 53 and 54:
Page 55 and 56:
ALVC selection table (cont.) TSSOP
Page 57 and 58:
LVT selection table (cont.) TSSOP S
Page 59 and 60:
AVC(M) LOGIC AVC and AVCM devices a
Page 61 and 62:
AUP selection table (cont.) VSSOP M
Page 63 and 64:
AXP LOGIC As the first logic family
Page 65 and 66:
Product listing by function Analog
Page 67 and 68:
Analog switches (cont.) Type number
Page 69 and 70:
Buffers-inverters-drivers (cont.) T
Page 71 and 72:
Page 73 and 74:
Page 75 and 76:
BUS SWITCHES Features and benefits
Page 77 and 78:
Counters/frequency dividers (cont.)
Page 79 and 80:
Decoders demultiplexers (cont.) Typ
Page 81 and 82:
Digital multiplexers (cont.) Type n
Page 83 and 84:
Flip-flops (cont.) Type number Desc
Page 85 and 86: Flip-flops (cont.) Type number Desc
Page 87 and 88: GATES This section includes AND gat
Page 89 and 90: Gates - Configurable Type number De
Page 91 and 92: Gates - NAND (cont.) Type number De
Page 93 and 94: Gates - OR (cont.) Type number Desc
Page 95 and 96: Latches-registered drivers (cont.)
Page 97 and 98: Level shifters-translators (cont.)
Page 99 and 100: PARITY GENERATORS/CHECKERS Features
Page 101 and 102: Schmitt triggers (cont.) Type numbe
Page 103 and 104: Shift registers - LED drivers (cont
Page 105 and 106: Transceivers (cont.) Type number De
Page 107 and 108: Q100 Standard Logic functions & pac
Page 109 and 110: Buffers/inverters (cont.) Features
Page 111 and 112: Counters/frequency dividers (cont.)
Page 113 and 114: Flip-flops (cont.) Features Package
Page 115 and 116: Gates (cont.) Features Package (suf
Page 117 and 118: Level shifters/translators Features
Page 119 and 120: Shift registers (cont.) Features Pa
Page 121 and 122: Standard logic packages Package suf
Page 123 and 124: Buffers/inverters (cont.) Features
Page 125 and 126: Digital decoders/demultiplexers Fea
Page 127 and 128: Gates (cont.) Features Package (suf
Page 129 and 130: Level shifters/translators Features
Page 131 and 132: The leadless advantage Today’s ul
Page 133 and 134: Nomenclature NXP's naming conventio
Page 135: SOT457 GV SOT505-2 DP Pinout Pinout
Page 139 and 140: SOT902-2 GM SOT996 GD Pinout Pinout
Page 141 and 142: SOT1089 GF SOT1202 GS Pinout Pinout
Page 143 and 144: SOT815-1 BQ SOT402-1 PW Pinout Pino
Page 145 and 146: SOT337-1 DB SOT338-1 DB Pinout Pino
Page 147 and 148: SOT724-1 DS SOT1174 GM Pinout Pinou
Page 149 and 150: SOT556-1 DK SOT340-1 DB Pinout Pino
Page 151 and 152: Design tools NXP is committed to ma
Page 153 and 154: Evaluation board for configurable l
Page 155 and 156: Toshiba one gate IDT logic TC7 S Z
show all

Logic selection guide 2016

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?