Logic selection guide 2016

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Low-voltage families This section includes the following low-voltage logic families, in ascending order of performance LV logic 46 LVC logic 48 ALVC logic 54 LVT logic 56 ALVT logic 58 AVC(M) logic 59 AUP logic 60 AXP logic 63 CBTLV(D) logic 64 LV LOGIC The LV family provides the performance of 5 V HCMOS within the supply range of 3.0 to 3.6 V. The typical operating range is from 1.0 to 3.6 V, but many functions are specified from 1.0 to 5.5 V, with low ground bounce and high reliability. Offering fully compatible TTL input levels and balanced propagation delays for high speed, LV devices deliver higher output drive and higher speed than 5 V HCMOS devices. The family is pin-compatible with HC(T) devices and is fully specified from -40 to +125 °C. Features and benefits 4 Wide operating voltage (1.0 to 5.5 V) 4 Optimized for low-voltage applications (1.0 to 3.6 V) 4 Accepts TTL input levels between V CC = 2.7 V and V CC = 3.6 V 4 Typical output ground bounce < 0.8 V at V CC = 3.3 V and T amb = 25 °C 4 Typical high-level output voltage 4 (V OH ) undershoot: > 2 V at V CC = 3.3 V and T amb = 25 °C Applications 4 Industrial control (linear amplifiers, crystal oscillators, etc.) 4 Battery back-up systems (chargers, UPS systems, etc.) 4 Electronic data-processing peripherals 4 Automotive electrical systems 46 NXP Logic selection guide 2016
LV selection table TSSOP SSOP SO DQFN Type number Function Description Suffix PW Suffix DB Suffix D Suffix BQ 74LV00 NAND gate Quad 2-input NAND gate • • • • 74LV02 NOR gate Quad 2-input NOR gate • • • 74LV03 NAND gate Quad 2-input NAND gate; open drain • 74LV04 Buffer/inverter/driver Hex inverter • 74LV08 AND gate Quad 2-input AND gate • • • 74LV123 Multivibrator Dual retriggerable monostable multivibrator with reset • • • • 74LV125 Buffer/inverter/driver Quad buffer/line driver (3-state) • • • 74LV132 Schmitt trigger Quad 2-input NAND gate Schmitt trigger • • • • 74LV138 Decoder/demultiplexer 3-to-8 line decoder/demultiplexer; inverting • • • • 74LV139 Decoder/demultiplexer Dual 2-to-4 line decoder/demultiplexer • • • • 74LV14 Schmitt trigger Hex inverter Schmitt trigger • • • • 74LV153 Digital multiplexer Dual 4-input multiplexer • • • 74LV164 Shift register 8-bit serial-in/parallel-out shift register • • • • 74LV165 Shift register 8-bit parallel or serial-in/serial-out shift register • • • 74LV165A Shift register 8-bit parallel or serial-in/serial-out shift register • • 74LV174 D-type flip-flop Hex D-type flip-flop with reset; positive-edge trigger • • • 74LV241 Buffer/inverter/driver Octal buffer/line driver (3-state) • • • 74LV244 Buffer/inverter/driver Octal buffer/line driver (3-state) • • • 74LV245 Transceiver Octal transceiver (3-state) • • • 74LV251 Digital multiplexer 8-input multiplexer (3-state) • • • 74LV259 Latch/registered driver 8 bit addressable latch • • • • 74LV27 NOR gate Triple 3-input NOR gate • 74LV273 D-type flip-flop Octal D-type flip-flop with reset; positive-edge trigger • • • 74LV32 OR gate Quad 2-input OR gate • • • • 74LV365 Buffer/inverter/driver Hex buffer/line driver (3-state) • • • 74LV367 Buffer/inverter/driver Hex buffer/line driver (3-state) • • • 74LV373 Latch/registered driver Octal D-type transparent latch (3-state) • • • 74LV374 D-type flip-flop Octal D-type flip-flop; positive-edge trigger (3-state) • • • 74LV377 D-type flip-flop Octal D-type flip-flop with data enable; positive-edge trigger • • • 74LV393 Binary counter/timer Dual 4-bit binary ripple counter • • • 74LV4020 Binary counter/timer 14-stage binary ripple counter • • • 74LV4051 Analog switch Single-pole, octal-throw analog switch • • • • 74LV4052 Analog switch Dual single-pole, quad-throw analog switch • • • 74LV4053 Analog switch Triple single-pole, double-throw analog switch • • • • 74LV4060 Binary counter/timer 14-stage binary ripple counter with oscillator • • • 74LV4066 Analog switch Quad single-pole, single-throw analog switch • • • 74LV4094 Shift register 8-bit serial-in/serial or parallel-out shift register with output register (3-state) • • • 74LV541 Buffer/inverter/driver Octal buffer/line driver (3-state) • • • 74LV573 Latch/registered driver Octal D-type transparent latch (3-state) • • • 74LV574 D-type flip-flop Octal D-type flip-flop; positive-edge trigger (3-state) • • • 74LV595 74LV74 Shift register D-type flip-flop 8-bit serial-in/parallel-out shift register with output storage register (3-state) Dual D-type flip-flop with set and reset; positive-edge trigger • • • • • • 74LV86 EXCLUSIVE-OR gate Quad 2-input EXCLUSIVE-OR gate • • • • 74LVU04 Buffer/inverter/driver Hex inverter; unbuffered • • • • NXP Logic selection guide 2016 47
Page 1 and 2: Logic selection guide 2016 Standard
Page 3 and 4: Standard Logic and Mini Logic: tune
Page 5 and 6: Transceivers 120 Standard logic pac
Page 7 and 8: NXP is the #1 volume leader For the
Page 9 and 10: What is configurable logic? Configu
Page 11 and 12: Our approach to quality At NXP, we
Page 13 and 14: Low-voltage families INCREASING PER
Page 15 and 16: Special features NXP offers a varie
Page 17 and 18: SOURCE TERMINATION What it does Imp
Page 19 and 20: OVERVOLTAGE-TOLERANT OUTPUTS 3-stat
Page 21 and 22: LIVE INSERTION What it does Enables
Page 23 and 24: OPEN-DRAIN OUTPUTS Open-drain outpu
Page 25 and 26: High-voltage families This section
Page 27 and 28: HEF4000B selection table (cont.) SO
Page 29 and 30: HC(T) selection table (cont.) TSSOP
Page 39 and 40: AHC(T) selection table (cont.) TSSO
Page 41 and 42: AHC(T) selection table (cont.) TSSO
Page 43 and 44: XC7 LOGIC XC7 devices are very high
Page 45: CBT(D) LOGIC CBT and CBTD bus switc
Page 49 and 50: LVC selection table (cont.) TSSOP V
Page 55 and 56: ALVC selection table (cont.) TSSOP
Page 57 and 58: LVT selection table (cont.) TSSOP S
Page 59 and 60: AVC(M) LOGIC AVC and AVCM devices a
Page 61 and 62: AUP selection table (cont.) VSSOP M
Page 63 and 64: AXP LOGIC As the first logic family
Page 65 and 66: Product listing by function Analog
Page 67 and 68: Analog switches (cont.) Type number
Page 69 and 70: Buffers-inverters-drivers (cont.) T
Page 75 and 76: BUS SWITCHES Features and benefits
Page 77 and 78: Counters/frequency dividers (cont.)
Page 79 and 80: Decoders demultiplexers (cont.) Typ
Page 81 and 82: Digital multiplexers (cont.) Type n
Page 83 and 84: Flip-flops (cont.) Type number Desc
Page 85 and 86: Flip-flops (cont.) Type number Desc
Page 87 and 88: GATES This section includes AND gat
Page 89 and 90: Gates - Configurable Type number De
Page 91 and 92: Gates - NAND (cont.) Type number De
Page 93 and 94: Gates - OR (cont.) Type number Desc
Page 95 and 96: Latches-registered drivers (cont.)
Page 97 and 98:
Level shifters-translators (cont.)
Page 99 and 100:
PARITY GENERATORS/CHECKERS Features
Page 101 and 102:
Schmitt triggers (cont.) Type numbe
Page 103 and 104:
Shift registers - LED drivers (cont
Page 105 and 106:
Transceivers (cont.) Type number De
Page 107 and 108:
Q100 Standard Logic functions & pac
Page 109 and 110:
Buffers/inverters (cont.) Features
Page 111 and 112:
Counters/frequency dividers (cont.)
Page 113 and 114:
Flip-flops (cont.) Features Package
Page 115 and 116:
Gates (cont.) Features Package (suf
Page 117 and 118:
Level shifters/translators Features
Page 119 and 120:
Shift registers (cont.) Features Pa
Page 121 and 122:
Standard logic packages Package suf
Page 123 and 124:
Buffers/inverters (cont.) Features
Page 125 and 126:
Digital decoders/demultiplexers Fea
Page 127 and 128:
Gates (cont.) Features Package (suf
Page 129 and 130:
Level shifters/translators Features
Page 131 and 132:
The leadless advantage Today’s ul
Page 133 and 134:
Nomenclature NXP's naming conventio
Page 135 and 136:
SOT457 GV SOT505-2 DP Pinout Pinout
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SOT765-1 DC SOT833-1 GT Pinout Pino
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SOT902-2 GM SOT996 GD Pinout Pinout
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SOT1089 GF SOT1202 GS Pinout Pinout
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SOT815-1 BQ SOT402-1 PW Pinout Pino
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SOT337-1 DB SOT338-1 DB Pinout Pino
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SOT724-1 DS SOT1174 GM Pinout Pinou
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SOT556-1 DK SOT340-1 DB Pinout Pino
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Design tools NXP is committed to ma
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Evaluation board for configurable l
Page 155 and 156:
Toshiba one gate IDT logic TC7 S Z
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