Logic selection guide 2016

Gates - Configurable
Type number Description V CC
(V)
Logic
switching
levels
Output
drive
capability
(mA)
t pd
(ns)
Output
Load
C L (Typ)
f max
(MHz)
Number
of bits
T amb
(°C)
74AUP1G57 Configurable gate; Schmitt trigger 1.1 to 3.6 CMOS 1.9 / -1.9 8.7 30 pF 70 1 -40 to +125
74AUP1G58 Configurable gate; Schmitt trigger 1.1 to 3.6 CMOS 1.9 / -1.9 8.7 30 pF 70 1 -40 to +125
74AUP1G97 Configurable gate; Schmitt trigger 1.1 to 3.6 CMOS 1.9 / -1.9 8.7 30 pF 70 1 -40 to +125
74AUP1G98 Configurable gate; Schmitt trigger 1.1 to 3.6 CMOS 1.9 / -1.9 8.9 30 pF 70 1 -40 to +125
74AUP1T57
74AUP1T58
74AUP1T97
74AUP1T98
Configurable gate with voltagelevel
translation
Configurable gate with voltagelevel
translation
Configurable gate with voltagelevel
translation
Configurable gate with voltagelevel
translation
2.3 to 3.6 CMOS 1.9 / -1.9 8.7 30 pF 70 1 -40 to +125
2.3 to 3.6 CMOS 1.9 / -1.9 8.7 30 pF 70 1 -40 to +125
2.3 to 3.6 CMOS 1.9 / -1.9 8.7 30 pF 70 1 -40 to +125
2.3 to 3.6 CMOS 1.9 / -1.9 8.7 30 pF 70 1 -40 to +125
74AXP1G57 Configurable gate; Schmitt trigger 0.7 to 2.75 CMOS 4.5 / -4.5 4.6 5pF 70 1 -40 to +85
74AXP1G58 Configurable gate; Schmitt trigger 0.7 to 2.75 CMOS 4.5 / -4.5 4.5 5pF 70 1 -40 to +85
74AXP1G97 Configurable gate; Schmitt trigger 0.7 to 2.75 CMOS 4.5 / -4.5 4.5 5pF 70 1 -40 to +85
74AXP1G98 Configurable gate; Schmitt trigger 0.7 to 2.75 CMOS 4.5 / -4.5 4.5 5pF 70 1 -40 to +85
74LVC1G57 Configurable gate; Schmitt trigger 1.65 to 5.5 TTL ±32 6.3 50 pF 150 1 -40 to +125
74LVC1G58 Configurable gate; Schmitt trigger 1.65 to 5.5 TTL ±32 6.3 50 pF 150 1 -40 to +125
74LVC1G97 Configurable gate; Schmitt trigger 1.65 to 5.5 TTL ±32 6.3 50 pF 150 1 -40 to +125
74LVC1G98 Configurable gate; Schmitt trigger 1.65 to 5.5 TTL ±32 6.3 50 pF 150 1 -40 to +125
74LVC1G99 Configurable gate; Schmitt trigger 1.65 to 5.5 TTL ±32 8.4 50 pF 150 1 -40 to +125
Gates - EXCLUSIVE-NOR
Type number Description V CC
(V)
Logic
switching
levels
Output
drive
capability
(mA)
t pd
(ns)
Output
Load
C L (Typ)
f max
(MHz)
T amb
(°C)
74HC7266 Quad 2-input EXCLUSIVE-NOR gate 2.0 to 6.0 CMOS ±5.2 11 50 pF 36 -40 to +125
HEF4077 Quad 2-input EXCLUSIVE-NOR gate 4.5 to 15.5 CMOS ±2.4 30 50 pF 10 -40 to +85
Gates - EXCLUSIVE-OR (cont.)
Type number Description V CC
(V)
Logic
switching
levels
Output
drive
capability
(mA)
t pd
(ns)
Output
Load
C L (Typ)
f max
(MHz)
Number
of bits
T amb
(°C)
74AHC1G86 2-input EXCLUSIVE-OR gate 2.0 to 5.5 CMOS ±8 3.4 50 pF 60 1 -40 to +125
74AHCT1G86
2-input EXCLUSIVE-OR gate;
TTL-enabled
4.5 to 5.5 TTL ±8 3.5 50 pF 60 1 -40 to +125
74AHC86 Quad 2-input EXCLUSIVE-OR gate 2.0 to 5.5 CMOS ±8 3.4 50 pF 60 4 -40 to +125
74AHCT86
Quad 2-input EXCLUSIVE-OR gate;
TTL-enabled
4.5 to 5.5 TTL ±8 3.4 50 pF 60 4 -40 to +125
74AUP1G386 Single 3-input EXCLUSIVE-OR gate 1.1 to 3.6 CMOS 1.9/-1.9 8.6 30 pF 70 1 -40 to +125
74AUP2G86 Dual 2-input EXCLUSIVE-OR gate 1.1 to 3.6 CMOS 1.9/-1.9 9 30 pF 70 2 -40 to +125
74HC1G86 Single 2-input EXCLUSIVE-OR gate 2.0 to 6.0 CMOS ±2.6 9 50 pF 36 1 -40 to +125
Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic.
NXP Logic selection guide 2016
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