Logic selection guide 2016

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Gates (cont.) Features Package (suffix) Type number Description V CC (V) I O (mA) t pd (ns) T amb (°C) SOT353-1 (GW) SOT753 (GV) SOT363 (GW) SOT457 (GV) SOT505-2 (DP) SOT765-1 (DC) 74AHC1G09-Q100 Single 2-input AND gate; open-drain 2.0 - 5.5 ± 8 3.2 -40~125 • • 74AHC1G00-Q100 Single 2-input NAND gate 2.0 - 5.5 ± 8 3.5 -40~125 • • 74AHCT1G00-Q100 Single 2-input NAND gate; TTL-enabled 4.5 - 5.5 ± 8 3.6 -40~125 • • 74AHC1G02-Q100 Single 2-input NOR gate 2.0 - 5.5 ± 8 3.2 -40~125 • • 74AHCT1G02-Q100 Single 2-input NOR gate; TTL-enabled 4.5 - 5.5 ± 8 3.5 -40~125 • • 74AHC1G08-Q100 Single 2-input AND gate 2.0 - 5.5 ± 8 3.2 -40~125 • • 74AHCT1G08-Q100 Single 2-input AND gate; TTL-enabled 4.5 - 5.5 ± 8 3.6 -40~125 • • 74AHC1G32-Q100 Single 2-input OR gate 2.0 - 5.5 ± 8 3.2 -40~125 • • 74AHCT1G32-Q100 Single 2-input OR gate; TTL-enabled 4.5 - 5.5 ± 8 3.3 -40~125 • • 74AHC1G86-Q100 2-input EXCLUSIVE-OR gate 2.0 - 5.5 ± 8 3.4 -40~125 • • 74AHCT1G86-Q100 2-input EXCLUSIVE-OR gate; TTL-enabled 4.5 - 5.5 ± 8 3.5 -40~125 • • 74AHC2G00-Q100 Dual 2-input NAND gate 2.0 - 5.5 ± 8 3.5 -40~125 • • 74AHCT2G00-Q100 Dual 2-input NAND gate; TTL-enabled 4.5 - 5.5 ± 8 3.6 -40~125 • • 74AHC2G08-Q100 Dual 2-input AND gate 2.0 - 5.5 ± 8 3.2 -40~125 • • 74AHCT2G08-Q100 Dual 2-Input AND gate; TTL-enabled 4.5 - 5.5 ± 8 3.6 -40~125 • • 74AHC2G32-Q100 Dual 2-input OR gate 2.0 - 5.5 ± 8 3.2 -40~125 • • 74AHCT2G32-Q100 Dual 2-input OR gate; TTL-enabled 4.5 - 5.5 ± 8 3.3 -40~125 • • 74AUP1G02-Q100 Single 2-input NOR gate 1.1 - 3.6 ± 1.9 8.2 -40~125 • 74AUP1G08-Q100 Single 2-input AND gate 1.1 - 3.6 ± 1.9 8.2 -40~125 • 74AUP1G32-Q100 Single 2-input OR gate 1.1 - 3.6 ±1.9 7.9 -40~125 • 74AUP1G86-Q100 Single 2-input EXCLUSIVE-OR gate 1.1 - 3.6 ± 1.9 3.3 -40~125 • 74AUP1T98-Q100 Configurable gate with voltage level translation 2.3-3.6 V ±1.9 8.7 -40~125 • 74HC1G86-Q100 Single 2-input EXCLUSIVE-OR gate 2.0 - 6.0 ± 2.6 9 -40~125 • • 74HC1GU04-Q100 Single inverter; unbuffered 2.0 - 6.0 ± 2.6 5 -40~125 • 74HC1G00-Q100 Single 2-input NAND gate 2.0 - 6.0 ± 2.6 7 -40~125 • 74HCT1G00-Q100 Single 2-input NAND gate; TTL-enabled 4.5 - 5.5 ± 2 10 -40~125 • • 74HC1G02-Q100 Single 2-input NOR gate 2.0 - 6.0 ± 2.6 7 -40~125 • • 74HCT1G02-Q100 Single 2-input NOR gate; TTL-enabled 4.5 - 5.5 ± 2.0 9 -40~125 • • 74HC1G08-Q100 Single 2-input AND gate 2.0 - 6.0 ± 5.2 7 -40~125 • • 74HCT1G08-Q100 Single 2-input AND gate; TTL-enabled 4.5 - 5.5 ± 2 11 -40~125 • • 74HC1G32-Q100 Single 2-input OR gate 2.0 - 6.0 ± 2.6 8 -40~125 • • 74HCT1G32-Q100 Single 2-input OR gate; TTL-enabled 4.5 - 5.5 ± 2.0 10 -40~125 • • 74HC2G00-Q100 Dual 2-input NAND gate 2.0 - 6.0 ± 5.6 9 -40~125 • • 126 NXP Logic selection guide 2016
Gates (cont.) Features Package (suffix) Type number Description V CC (V) I O (mA) t pd (ns) T amb (°C) SOT353-1 (GW) SOT753 (GV) SOT363 (GW) SOT457 (GV) SOT505-2 (DP) SOT765-1 (DC) 74HCT2G00-Q100 Dual 2-input NAND gate; TTL-enabled 4.5 - 5.5 ± 4 12 -40~125 • • 74HC2G02-Q100 Dual 2-input NOR gate 2.0 - 6.0 ± 5.2 9 -40~125 • • 74HCT2G02-Q100 Dual 2-input NOR gate; TTL-enabled 4.5 - 5.5 ± 4 12 -40~125 • • 74HC2G08-Q100 Dual 2-input AND gate 2.0 - 6.0 ± 5.2 9 -40~125 • • 74HCT2G08-Q100 Dual 2-Input AND gate; TTL-enabled 4.5 - 5.5 ± 4 14 -40~125 • • 74HC2G32-Q100 Dual 2-input OR gate 2.0 - 6.0 ± 5.2 9 -40~125 • • 74HCT2G32-Q100 Dual 2-input OR gate; TTL-enabled 4.5 - 5.5 ± 4.0 13 -40~125 • • 74HC2G86-Q100 Dual 2-input EXCLUSIVE-OR gate 2.0 - 6.0 ± 5.2 9 -40~125 • • 74HCT2G86-Q100 74HCT1G86-Q100 Dual 2-input EXCLUSIVE-OR gate; TTL-enabled Single 2-input EXCLUSIVE-OR gate; TTL-enabled 4.5 - 5.5 ± 4.0 11 -40~125 • • 4.5 - 5.5 ± 2.0 10 -40~125 • • 74LVC1G00-Q100 Single 2-input NAND gate 1.65 - 5.5 ± 32 2.2 -40~125 • • 74LVC1G02-Q100 Single 2-input NOR gate 1.65 - 5.5 ± 32 2.1 -40~125 • • 74LVC1G08-Q100 Single 2-input AND gate 1.65 - 5.5 ± 32 2.1 -40~125 • • 74LVC1G11-Q100 Single 3-input AND gate 1.65 - 5.5 ± 32 2.6 -40~125 • • 74LVC1G32-Q100 Single 2-input OR gate 1.65 - 5.5 ± 32 2.1 -40~125 • • 74LVC1G38-Q100 Single 2-input NAND gate; open-drain 1.65 - 5.5 32 2.3 -40~125 • • 74LVC1G57-Q100 Configurable gate; Schmitt trigger 1.65 - 5.5 ± 32 3.8 -40~125 • • 74LVC1G58-Q100 Configurable gate; Schmitt trigger 1.65 - 5.5 ± 32 3.8 -40~125 • • 74LVC1G86-Q100 Single 2-input EXCLUSIVE-OR gate 1.65 - 5.5 ± 32 2.4 -40~125 • • 74LVC1G332-Q100 Single 3-input OR gate 1.65 - 5.5 ± 32 2.6 -40~125 • • 74LVC1GX04-Q100 Crystal driver 1.65 - 5.5 ± 24 2.8 -40~125 • • 74LVC2G02-Q100 Dual 2-input NOR gate 1.65 - 5.5 ± 32 2.4 -40~125 • • 74LVC2G08-Q100 Dual 2-input AND gate 1.65 - 5.5 ± 24 2.1 -40~125 • • 74LVC2G32-Q100 Dual 2-input OR gate 1.65 - 5.5 ± 32 2.2 -40~125 • • 74LVC2G34-Q100 Dual buffer 1.65 - 5.5 ± 32 2.2 -40~125 • • 74LVC2G86-Q100 Dual 2-input EXCLUSIVE-OR gate 1.65 - 5.5 ± 32 2.3 -40~125 • • NXP Logic selection guide 2016 127
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Logic selection guide 2016 Standard
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Standard Logic and Mini Logic: tune
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Transceivers 120 Standard logic pac
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NXP is the #1 volume leader For the
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What is configurable logic? Configu
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Our approach to quality At NXP, we
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Low-voltage families INCREASING PER
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Special features NXP offers a varie
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SOURCE TERMINATION What it does Imp
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OVERVOLTAGE-TOLERANT OUTPUTS 3-stat
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LIVE INSERTION What it does Enables
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OPEN-DRAIN OUTPUTS Open-drain outpu
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High-voltage families This section
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HEF4000B selection table (cont.) SO
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HC(T) selection table (cont.) TSSOP
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AHC(T) selection table (cont.) TSSO
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AHC(T) selection table (cont.) TSSO
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XC7 LOGIC XC7 devices are very high
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CBT(D) LOGIC CBT and CBTD bus switc
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LV selection table TSSOP SSOP SO DQ
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LVC selection table (cont.) TSSOP V
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ALVC selection table (cont.) TSSOP
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LVT selection table (cont.) TSSOP S
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AVC(M) LOGIC AVC and AVCM devices a
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AUP selection table (cont.) VSSOP M
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AXP LOGIC As the first logic family
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Product listing by function Analog
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Analog switches (cont.) Type number
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Buffers-inverters-drivers (cont.) T
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Page 75 and 76: BUS SWITCHES Features and benefits
Page 77 and 78: Counters/frequency dividers (cont.)
Page 79 and 80: Decoders demultiplexers (cont.) Typ
Page 81 and 82: Digital multiplexers (cont.) Type n
Page 83 and 84: Flip-flops (cont.) Type number Desc
Page 85 and 86: Flip-flops (cont.) Type number Desc
Page 87 and 88: GATES This section includes AND gat
Page 89 and 90: Gates - Configurable Type number De
Page 91 and 92: Gates - NAND (cont.) Type number De
Page 93 and 94: Gates - OR (cont.) Type number Desc
Page 95 and 96: Latches-registered drivers (cont.)
Page 97 and 98: Level shifters-translators (cont.)
Page 99 and 100: PARITY GENERATORS/CHECKERS Features
Page 101 and 102: Schmitt triggers (cont.) Type numbe
Page 103 and 104: Shift registers - LED drivers (cont
Page 105 and 106: Transceivers (cont.) Type number De
Page 107 and 108: Q100 Standard Logic functions & pac
Page 109 and 110: Buffers/inverters (cont.) Features
Page 111 and 112: Counters/frequency dividers (cont.)
Page 113 and 114: Flip-flops (cont.) Features Package
Page 115 and 116: Gates (cont.) Features Package (suf
Page 117 and 118: Level shifters/translators Features
Page 119 and 120: Shift registers (cont.) Features Pa
Page 121 and 122: Standard logic packages Package suf
Page 123 and 124: Buffers/inverters (cont.) Features
Page 125: Digital decoders/demultiplexers Fea
Page 129 and 130: Level shifters/translators Features
Page 131 and 132: The leadless advantage Today’s ul
Page 133 and 134: Nomenclature NXP's naming conventio
Page 135 and 136: SOT457 GV SOT505-2 DP Pinout Pinout
Page 137 and 138: SOT765-1 DC SOT833-1 GT Pinout Pino
Page 139 and 140: SOT902-2 GM SOT996 GD Pinout Pinout
Page 141 and 142: SOT1089 GF SOT1202 GS Pinout Pinout
Page 143 and 144: SOT815-1 BQ SOT402-1 PW Pinout Pino
Page 145 and 146: SOT337-1 DB SOT338-1 DB Pinout Pino
Page 147 and 148: SOT724-1 DS SOT1174 GM Pinout Pinou
Page 149 and 150: SOT556-1 DK SOT340-1 DB Pinout Pino
Page 151 and 152: Design tools NXP is committed to ma
Page 153 and 154: Evaluation board for configurable l
Page 155 and 156: Toshiba one gate IDT logic TC7 S Z
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