Logic selection guide 2016

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LVC LOGIC LVC logic is specified over 1.65 to 3.6 V in standard formats, and from 1.65 to 5.5 V in PicoGate packages. With a balanced output drive of 24 mA and a typical propagation delay of 2 ns, and an extensive set of special features, the LVC family is well suited for parallel-interface applications. All LVC devices are fully specified from -40 to 125 °C. Features and benefits 4 Typical propagation delay of 2 ns 4 Output drive capability I OH / I OL = ±24 mA 4 Low power 4 5 V-tolerant I/O 4 Live insertion/extraction permitted 4 Buffers and drivers with 30 Ω integrated series termination (optional) 4 Bus hold on data inputs (optional) 4 Bus-interface functions in 16- and 32-bit versions Applications 4 STBs, DVD players, HDTVs 4 Workstations 4 Telecom and networking equipment 4 Advanced bus interfaces 4 Computer peripherals LVC selection table (cont.) TSSOP VSSOP SSOP SO DQFN BGA MicroPak PicoGate Type number Function Description 74LVC162244A 74LVCH162244A 74LVC162245A 74LVCH162245A 74LVC162373A 74LVCH162373A 74LVC16244A 74LVCH16244A Buffer/inverter/ driver Buffer/inverter/ driver Transceiver Transceiver Latch/registered driver Latch/registered driver Buffer/inverter/ driver Buffer/inverter/ driver 16-bit buffer/line driver with 30 Ω termination resistors (3-state) 16-bit buffer/line driver with bus hold and 30 Ω termination resistors (3-state) 16-bit transceiver with 30 Ω termination resistors (3-state) 16-bit transceiver with bus hold and 30 Ω termination resistors (3-state) 16-bit D-type transparent latch with 30 Ω termination resistors (3-state) 16-bit D-type transparent latch with bus hold and 30 Ω termination resistors (3-state) 16-bit buffer/line driver (3-state) 16-bit buffer/line driver with bus hold (3-state) Suffix DGG, PW Suffix DC Suffix DB, DL • • • • • • • • • • • • Suffix D Suffix BQ, BX Suffix EC, EV • • • • 74LVC16245A Transceiver 16-bit transceiver (3-state) • • • 74LVCH16245A 74LVC16373A 74LVCH16373A 74LVC16374A 74LVCH16374A 74LVC1T45 Transceiver Latch/registered driver Latch/registered driver D-type flip-flop D-type flip-flop Level shifter/ translator 16-bit transceiver with bus hold (3-state) 16-bit D-type transparent latch (3-state) 16-bit D-type transparent latch with bus hold (3-state) 16-bit D-type flip-flop; positive-edge trigger (3-state) 16-bit D-type flip-flop with bus hold; positive-edge trigger (3-state) Single dual-supply voltagetranslating transceiver (3-state) • • • • • • • • • • • • • • • Suffix GD, GF, GM, GN, GS, GT, GX Suffix DP, GW, GV • • 48 NXP Logic selection guide 2016
LVC selection table (cont.) TSSOP VSSOP SSOP SO DQFN BGA MicroPak PicoGate Type number Function Description 74LVCH1T45 74LVC244A 74LVCH244A Level shifter/ translator Buffer/inverter/ driver Buffer/inverter/ driver Single dual-supply voltagetranslating transceiver with bus hold (3-state) Octal buffer/line driver (3-state) Octal buffer/line driver with bus hold (3-state) Suffix DGG, PW Suffix DC Suffix DB, DL Suffix D Suffix BQ, BX • • • • • • • • 74LVC245A Transceiver Octal transceiver (3-state) • • • • 74LVCH245A 74LVC2T45 74LVCH2T45 74LVC8T245 Transceiver Level shifter/ translator Level shifter/ translator Level shifter/ translator Octal transceiver with bus hold (3-state) Dual-bit dual-supply voltagetranslating transceiver (3-state) Dual-bit dual-supply voltagetranslating transceiver with bus hold (3-state) 8-bit dual-supply voltagetranslating transceiver (3-state) • • • • Suffix EC, EV Suffix GD, GF, GM, GN, GS, GT, GX • • • • • • 74LVC00A NAND gate Quad 2-input NAND gate • • • • 74LVC02A NOR gate Quad 2-input NOR gate • • • • 74LVC04A 74LVC06A 74LVC07A Buffer/inverter/ driver Buffer/inverter/ driver Buffer/inverter/ driver Hex inverter • • • • Hex inverter; open drain • • • Hex buffer; open drain • • • 74LVC08A AND gate Quad 2-input AND gate • • • • 74LVC109 JK-type flip-flop Dual J-/K flip-flop with set and reset; positive-edge trigger • • • 74LVC10A NAND gate Triple 3-input NAND gate • • • • 74LVC11 AND gate Triple 3-input AND gate • • • • 74LVC125A 74LVC126A 74LVC132A 74LVC138A 74LVC139 Buffer/inverter/ driver Buffer/inverter/ driver Schmitt trigger Decoder/ demultiplexer Decoder/ demultiplexer Quad buffer/line driver (3-state) Quad buffer/line driver (3-state) Quad 2-input NAND gate Schmitt trigger 3-to-8 line decoder/ demultiplexer; inverting Dual 2-to-4 line decoder/ demultiplexer • • • • • • • • • • • • • • • • • • • 74LVC14A Schmitt trigger Hex inverter Schmitt trigger • • • • 74LVC157A 74LVC161 74LVC16240A 74LVC16241A 74LVC163 Digital multiplexer Binary counter/ timer Buffer/inverter/ driver Buffer/inverter/ driver Binary counter/ timer Quad 2-input multiplexer • • • • Presettable synchronous 4-bit binary counter; asynchronous reset 16-bit inverter/line driver (3-state) 16-bit buffer/line driver (3-state) Presettable synchronous 4-bit binary counter; synchronous reset • • • • • • • • • • • • Suffix DP, GW, GV • • NXP Logic selection guide 2016 49
Page 1 and 2: Logic selection guide 2016 Standard
Page 3 and 4: Standard Logic and Mini Logic: tune
Page 5 and 6: Transceivers 120 Standard logic pac
Page 7 and 8: NXP is the #1 volume leader For the
Page 9 and 10: What is configurable logic? Configu
Page 11 and 12: Our approach to quality At NXP, we
Page 13 and 14: Low-voltage families INCREASING PER
Page 15 and 16: Special features NXP offers a varie
Page 17 and 18: SOURCE TERMINATION What it does Imp
Page 19 and 20: OVERVOLTAGE-TOLERANT OUTPUTS 3-stat
Page 21 and 22: LIVE INSERTION What it does Enables
Page 23 and 24: OPEN-DRAIN OUTPUTS Open-drain outpu
Page 25 and 26: High-voltage families This section
Page 27 and 28: HEF4000B selection table (cont.) SO
Page 29 and 30: HC(T) selection table (cont.) TSSOP
Page 39 and 40: AHC(T) selection table (cont.) TSSO
Page 41 and 42: AHC(T) selection table (cont.) TSSO
Page 43 and 44: XC7 LOGIC XC7 devices are very high
Page 45 and 46: CBT(D) LOGIC CBT and CBTD bus switc
Page 47: LV selection table TSSOP SSOP SO DQ
Page 51 and 52: LVC selection table (cont.) TSSOP V
Page 53 and 54: LVC selection table (cont.) TSSOP V
Page 55 and 56: ALVC selection table (cont.) TSSOP
Page 57 and 58: LVT selection table (cont.) TSSOP S
Page 59 and 60: AVC(M) LOGIC AVC and AVCM devices a
Page 61 and 62: AUP selection table (cont.) VSSOP M
Page 63 and 64: AXP LOGIC As the first logic family
Page 65 and 66: Product listing by function Analog
Page 67 and 68: Analog switches (cont.) Type number
Page 69 and 70: Buffers-inverters-drivers (cont.) T
Page 75 and 76: BUS SWITCHES Features and benefits
Page 77 and 78: Counters/frequency dividers (cont.)
Page 79 and 80: Decoders demultiplexers (cont.) Typ
Page 81 and 82: Digital multiplexers (cont.) Type n
Page 83 and 84: Flip-flops (cont.) Type number Desc
Page 85 and 86: Flip-flops (cont.) Type number Desc
Page 87 and 88: GATES This section includes AND gat
Page 89 and 90: Gates - Configurable Type number De
Page 91 and 92: Gates - NAND (cont.) Type number De
Page 93 and 94: Gates - OR (cont.) Type number Desc
Page 95 and 96: Latches-registered drivers (cont.)
Page 97 and 98: Level shifters-translators (cont.)
Page 99 and 100:
PARITY GENERATORS/CHECKERS Features
Page 101 and 102:
Schmitt triggers (cont.) Type numbe
Page 103 and 104:
Shift registers - LED drivers (cont
Page 105 and 106:
Transceivers (cont.) Type number De
Page 107 and 108:
Q100 Standard Logic functions & pac
Page 109 and 110:
Buffers/inverters (cont.) Features
Page 111 and 112:
Counters/frequency dividers (cont.)
Page 113 and 114:
Flip-flops (cont.) Features Package
Page 115 and 116:
Gates (cont.) Features Package (suf
Page 117 and 118:
Level shifters/translators Features
Page 119 and 120:
Shift registers (cont.) Features Pa
Page 121 and 122:
Standard logic packages Package suf
Page 123 and 124:
Buffers/inverters (cont.) Features
Page 125 and 126:
Digital decoders/demultiplexers Fea
Page 127 and 128:
Gates (cont.) Features Package (suf
Page 129 and 130:
Level shifters/translators Features
Page 131 and 132:
The leadless advantage Today’s ul
Page 133 and 134:
Nomenclature NXP's naming conventio
Page 135 and 136:
SOT457 GV SOT505-2 DP Pinout Pinout
Page 137 and 138:
SOT765-1 DC SOT833-1 GT Pinout Pino
Page 139 and 140:
SOT902-2 GM SOT996 GD Pinout Pinout
Page 141 and 142:
SOT1089 GF SOT1202 GS Pinout Pinout
Page 143 and 144:
SOT815-1 BQ SOT402-1 PW Pinout Pino
Page 145 and 146:
SOT337-1 DB SOT338-1 DB Pinout Pino
Page 147 and 148:
SOT724-1 DS SOT1174 GM Pinout Pinou
Page 149 and 150:
SOT556-1 DK SOT340-1 DB Pinout Pino
Page 151 and 152:
Design tools NXP is committed to ma
Page 153 and 154:
Evaluation board for configurable l
Page 155 and 156:
Toshiba one gate IDT logic TC7 S Z
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