Logic selection guide 2016

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FIFO REGISTERS Features and benefits 4 Wide range of supply voltages 4 Independent asynchronous and synchronous inputs and outputs 4 Cascadable 4 Optional TTL inputs, 3-state outputs Applications 4 Data buffers FIFO registers Type number Description V CC (V) Logic switching levels Output drive capability (mA) t pd (ns) Output Load C L (Typ) f max (MHz) T amb (°C) 74HC40105 4-bit x 16-word FIFO register 2.0 to 6.0 CMOS Low 15 50 pF 30 -40 to +125 74HCT40105 4-bit x 16-word FIFO register; TTL-enabled 4.5 to 5.5 TTL ±4 mA 18 50 pF 28 -40 to +125 74HC7030 9-bit x 64-word FIFO register (3-state) 2.0 to 6.0 CMOS ±5.2 mA 36 50 pF 33 -40 to +125 74HCT7030 9-bit x 64-word FIFO register; TTL-enabled (3-state) 4.5 to 5.5 TTL ±4 mA 26 50 pF 29 -40 to +125 74HC7403 4-bit x 16-word FIFO register (3-state) 2.0 to 6.0 CMOS ±5.2 mA 15 50 pF 30 -40 to +125 74HCT7403 4-bit x 16-word FIFO register; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 mA 17 50 pF 30 -40 to +125 FLIP-FLOPS Features and benefits 4 Mixed 3.3/5 V applications 4 Improved signal integrity with integrated termination resistors 4 Flow-through pinout for easy layout 4 Wide range of supply voltage 4 Low propagation delay 4 Optional overvoltage-tolerant inputs, integrated sourcetermination resistors, bus hold Applications 4 Frequency division 4 Controlled delays 4 Interface between asynchronous and synchronous systems Flip-flops (cont.) Type number Description V CC (V) Logic switching levels Output drive capability (mA) t pd (ns) Output Load C L (Typ) f max (MHz) T amb (°C) 74AHC1G79 Single D-type flip-flop; positive-edge trigger 2.0 to 5.5 CMOS ±8 3,5 50 pF 90 -40 to +125 74AHCT1G79 74AHC273 74AHCT273 Single D-type flip-flop; positive-edge trigger; TTL-enabled Octal D-type flip-flop with reset; positive-edge trigger Octal D-type flip-flop with reset; positive-edge trigger; TTL-enabled 4.5 to 5.5 TTL ±8 3,5 50 pF 90 -40 to +125 2.0 to 5.5 CMOS ±8 4,2 50 pF 165 -40 to +125 4.5 to 5.5 TTL ±8 4 50 pF 120 -40 to +125 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. 82 NXP Logic selection guide 2016
Flip-flops (cont.) Type number Description V CC (V) 74AHC374 74AHCT374 74AHC377 74AHCT377 74AHC574 74AHCT574 74AHC74 74AHCT74 74ALVC374 74ALVC574 74ALVC74 74ALVCH16374 74ALVCH16821 74ALVCH16823 74ALVT162821 74ALVT162823 74ALVT16374 74ALVT16821 74ALVT16823 74AUP1G175 74AUP1G374 74AUP1G74 Octal D-type flip-flop; positive-edge trigger (3-state) Octal D-type flip-flop; positive-edge trigger (3-state) Octal D-type flip-flop with data enable; positiveedge trigger Octal D-type flip-flop with data enable; positiveedge trigger; TTL-enabled Octal D-type flip-flop; positive-edge trigger (3-state) Octal D-type flip-flop; positive-edge trigger; TTL-enabled (3-state) Dual D-type flip-flop with set and reset; positiveedge trigger Dual D-type flip-flop with set and reset; positiveedge trigger; TTL-enabled Octal D-type flip-flop; positive-edge trigger (3-state) Octal D-type flip-flop; positive-edge trigger (3-state) Dual D-type flip-flop with set and reset; positiveedge trigger 16-bit D-type flip-flop with bus hold; positiveedge trigger (3-state) 20-bit D-type flip-flop; positive-edge trigger (3-state) 18-bit D-type flip-flop with bus hold; positiveedge trigger (3-state) 20-bit D-type flip-flop; positive-edge trigger (3-state) 18-bit buffer/line driver with bus hold and 30 Ω termination resistors (3-state) 16-bit D-type flip-flop with bus hold; positiveedge trigger (3-state) 20-bit D-type flip-flop; positive-edge trigger (3-state) 18-bit D-type flip-flop with bus hold; positiveedge trigger (3-state) Single D flip-flop with reset; positive-edge trigger Single D-type flip-flop; positive-edge trigger (3-state) Single D-type flip-flop with set and reset; positive-edge trigger Logic switching levels Output drive capability (mA) t pd (ns) Output Load C L (Typ) f max (MHz) T amb (°C) 2.0 to 5.5 CMOS ±8 4,4 50 pF 185 -40 to +125 4.5 to 5.5 TTL ±8 4,3 50 pF 140 -40 to +125 2.0 to 5.5 CMOS ±8 3,9 50 pF 175 -40 to +125 4.5 to 5.5 TTL ±8 4 50 pF 140 -40 to +125 2.0 to 5.5 CMOS ±8 4,4 50 pF 130 -40 to +125 4.5 to 5.5 TTL ±8 4,4 50 pF 130 -40 to +125 2.0 to 5.5 CMOS ±8 3,7 50 pF 170 -40 to +125 4.5 to 5.5 TTL ±8 3,3 50 pF 160 -40 to +125 1.65 to 3.6 TTL ±24 2,5 50 pF 300 -40 to +85 1.65 to 3.6 TTL ±24 2,5 50 pF 300 -40 to +85 1.65 to 3.6 TTL ±24 2,3 50 pF 425 -40 to +85 1.2 to 3.6 TTL ±24 2,3 50 pF 350 -40 to +85 2.3 to 3.6 TTL ±24 2,5 50 pF 350 -40 to +85 1.2 to 3.6 TTL ±24 2,1 50 pF 350 -40 to +85 2.3 to 3.6 TTL ±12 3,2 50 pF 150 -40 to +85 2.3 to 3.6 TTL ±12 3 50 pF 150 -40 to +85 2.3 to 3.6 TTL -32/+64 2,3 50 pF 250 -40 to +85 2.3 to 3.6 TTL -32/+64 1,8 50 pF 150 -40 to +85 2.3 to 3.6 TTL -32/+64 1,9 50 pF 250 -40 to +85 1.1 to 3.6 CMOS ±1.9 7,4 30 pF 70 -40 to +125 1.1 to 3.6 CMOS ±1.9 7,9 30 pF 400 -40 to +125 1.1 to 3.6 CMOS ±1.9 9,2 30 pF 400 -40 to +125 74AUP1G79 Single D-type flip-flop; positive-edge trigger 1.1 to 3.6 CMOS ±1.9 9,1 30 pF 400 -40 to +125 74AUP1G80 Single D-type flip-flop; positive-edge trigger 1.1 to 3.6 CMOS ±1.9 9,1 30 pF 400 -40 to +125 74AUP2G79 Dual D-type flip-flop; positive-edge trigger 1.1 to 3.6 CMOS ±1.9 8,5 30 pF 400 -40 to +125 74AUP2G80 Dual D-type flip-flop; positive-edge trigger 1.1 to 3.6 CMOS ±1.9 9,1 30 pF 400 -40 to +125 74AVC16374 16-bit D-type flip-flop; positive-edge trigger (3-state) 1.2 to 3.6 CMOS ±12 1,5 30 pF 350 -40 to +85 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. NXP Logic selection guide 2016 83
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Logic selection guide 2016 Standard
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Standard Logic and Mini Logic: tune
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Transceivers 120 Standard logic pac
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NXP is the #1 volume leader For the
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What is configurable logic? Configu
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Our approach to quality At NXP, we
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Low-voltage families INCREASING PER
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Special features NXP offers a varie
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SOURCE TERMINATION What it does Imp
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OVERVOLTAGE-TOLERANT OUTPUTS 3-stat
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LIVE INSERTION What it does Enables
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OPEN-DRAIN OUTPUTS Open-drain outpu
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High-voltage families This section
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HEF4000B selection table (cont.) SO
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HC(T) selection table (cont.) TSSOP
Page 31 and 32: HC(T) selection table (cont.) TSSOP
Page 39 and 40: AHC(T) selection table (cont.) TSSO
Page 41 and 42: AHC(T) selection table (cont.) TSSO
Page 43 and 44: XC7 LOGIC XC7 devices are very high
Page 45 and 46: CBT(D) LOGIC CBT and CBTD bus switc
Page 47 and 48: LV selection table TSSOP SSOP SO DQ
Page 49 and 50: LVC selection table (cont.) TSSOP V
Page 55 and 56: ALVC selection table (cont.) TSSOP
Page 57 and 58: LVT selection table (cont.) TSSOP S
Page 59 and 60: AVC(M) LOGIC AVC and AVCM devices a
Page 61 and 62: AUP selection table (cont.) VSSOP M
Page 63 and 64: AXP LOGIC As the first logic family
Page 65 and 66: Product listing by function Analog
Page 67 and 68: Analog switches (cont.) Type number
Page 69 and 70: Buffers-inverters-drivers (cont.) T
Page 75 and 76: BUS SWITCHES Features and benefits
Page 77 and 78: Counters/frequency dividers (cont.)
Page 79 and 80: Decoders demultiplexers (cont.) Typ
Page 81: Digital multiplexers (cont.) Type n
Page 85 and 86: Flip-flops (cont.) Type number Desc
Page 87 and 88: GATES This section includes AND gat
Page 89 and 90: Gates - Configurable Type number De
Page 91 and 92: Gates - NAND (cont.) Type number De
Page 93 and 94: Gates - OR (cont.) Type number Desc
Page 95 and 96: Latches-registered drivers (cont.)
Page 97 and 98: Level shifters-translators (cont.)
Page 99 and 100: PARITY GENERATORS/CHECKERS Features
Page 101 and 102: Schmitt triggers (cont.) Type numbe
Page 103 and 104: Shift registers - LED drivers (cont
Page 105 and 106: Transceivers (cont.) Type number De
Page 107 and 108: Q100 Standard Logic functions & pac
Page 109 and 110: Buffers/inverters (cont.) Features
Page 111 and 112: Counters/frequency dividers (cont.)
Page 113 and 114: Flip-flops (cont.) Features Package
Page 115 and 116: Gates (cont.) Features Package (suf
Page 117 and 118: Level shifters/translators Features
Page 119 and 120: Shift registers (cont.) Features Pa
Page 121 and 122: Standard logic packages Package suf
Page 123 and 124: Buffers/inverters (cont.) Features
Page 125 and 126: Digital decoders/demultiplexers Fea
Page 127 and 128: Gates (cont.) Features Package (suf
Page 129 and 130: Level shifters/translators Features
Page 131 and 132: The leadless advantage Today’s ul
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Nomenclature NXP's naming conventio
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SOT457 GV SOT505-2 DP Pinout Pinout
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SOT765-1 DC SOT833-1 GT Pinout Pino
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SOT902-2 GM SOT996 GD Pinout Pinout
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SOT1089 GF SOT1202 GS Pinout Pinout
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SOT815-1 BQ SOT402-1 PW Pinout Pino
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SOT337-1 DB SOT338-1 DB Pinout Pino
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SOT724-1 DS SOT1174 GM Pinout Pinou
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SOT556-1 DK SOT340-1 DB Pinout Pino
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Design tools NXP is committed to ma
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Evaluation board for configurable l
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Toshiba one gate IDT logic TC7 S Z
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