Logic selection guide 2016

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Flip-flops (cont.) Type number Description V CC (V) 74HC107 74HCT107 74HC109 74HCT109 74HC112 74HCT112 74HC173 74HCT173 74HC174 74HCT174 74HC175 74HCT175 74HC273 74HCT273 74HC374 74HCT374 74HC377 74HCT377 74HC574 74HCT574 74HC74 74HCT74 74HC73 74HCT534 74HCT7273 Dual JK-type flip-flop with reset; negative-edge trigger Dual JK-type flip-flop with reset; negative-edge trigger; TTL-enabled Dual JK-type flip-flop with set and reset; positive-edge trigger Dual JK-type flip-flop with set and reset; positive-edge trigger; TTL-enabled Dual JK-type flip-flop with set and reset; negative-edge trigger Dual JK-type flip-flop with set and reset; negative-edge trigger; TTL-enabled Quad D-type flip-flop; positive-edge trigger (3-state) Quad D-type flip-flop; positive-edge trigger; TTL-enabled (3-state) Hex D-type flip-flop with reset; positive-edge trigger Hex D-type flip-flop with reset; positive-edge trigger; TTL-enabled Quad D-type flip-flop with reset; positive-edge trigger Quad D-type flip-flop with reset; positive-edge trigger; TTL-enabled Octal D-type flip-flop with reset; positive-edge trigger Octal D-type flip-flop with reset; positive-edge trigger; TTL-enabled Octal D-type flip-flop; positive-edge trigger (3-state) Octal D-type flip-flop; positive-edge trigger; TTL-enabled (3-state) Octal D-type flip-flop with data enable; positiveedge trigger Octal D-type flip-flop with data enable; positiveedge trigger; TTL-enabled Octal D-type flip-flop; positive-edge trigger (3-state) Octal D-type flip-flop; positive-edge trigger; TTL-enabled (3-state) Dual D-type flip-flop with set and reset; positiveedge trigger Dual D-type flip-flop with set and reset; positiveedge trigger; TTL-enabled Dual JK-type flip-flop with reset; negative-edge trigger Octal D-type flip-flop; inverting; positive-edge trigger; TTL-enabled (3-state) Octal D-type flip-flop with reset; positive edgetrigger; open drain outputs; TTL-enabled Logic switching levels Output drive capability (mA) t pd (ns) Output Load C L (Typ) f max (MHz) T amb (°C) 2.0 to 6.0 CMOS ±5.2 16 50 pF 78 -40 to +125 4.5 to 5.5 TTL ±4 16 50 pF 73 -40 to +125 2.0 to 6.0 CMOS ±5.2 15 50 pF 75 -40 to +125 4.5 to 5.5 TTL ±4 17 50 pF 61 -40 to +125 2.0 to 6.0 CMOS ±5.2 15 50 pF 66 -40 to +125 4.5 to 5.5 TTL ±4 19 50 pF 70 -40 to +125 2.0 to 6.0 CMOS ±7.8 17 50 pF 88 -40 to +125 4.5 to 5.5 TTL ±6 17 50 pF 88 -40 to +125 2.0 to 6.0 CMOS ±5.2 17 50 pF 99 -40 to +125 4.5 to 5.5 TTL ±4 18 50 pF 69 -40 to +125 2.0 to 6.0 CMOS ±5.2 17 50 pF 83 -40 to +125 4.5 to 5.5 TTL ±4 16 50 pF 54 -40 to +125 2.0 to 6.0 CMOS ±5.2 15 50 pF 122 -40 to +125 4.5 to 5.5 TTL ±4 15 50 pF 36 -40 to +125 2.0 to 6.0 CMOS ±7.8 14 50 pF 83 -40 to +125 4.5 to 5.5 TTL ±6 13 50 pF 48 -40 to +125 2.0 to 6.0 CMOS ±7.8 13 50 pF 83 -40 to +125 4.5 to 5.5 TTL ±6 14 50 pF 53 -40 to +125 2.0 to 6.0 CMOS ±7.8 14 50 pF 133 -40 to +125 4.5 to 5.5 TTL ±6 15 50 pF 76 -40 to +125 2.0 to 6.0 CMOS ±5.2 14 50 pF 82 -40 to +125 4.5 to 5.5 TTL ±4 15 50 pF 59 -40 to +125 2.0 to 6.0 CMOS ±5.2 16 50 pF 77 -40 to +125 4.5 to 5.5 TTL ±6 13 50 pF 40 -40 to +125 4.5 to 5.5 TTL 4 16 50 pF 56 -40 to +125 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. 84 NXP Logic selection guide 2016
Flip-flops (cont.) Type number Description V CC (V) 74LV174 74LV273 74LV374 74LV377 74LV574 74LV74 74LVC16374 74LVCH16374 74LVC109 74LVC1G175 74LVC1G74 Hex D-type flip-flop with reset; positive-edge trigger Octal D-type flip-flop with reset; positive-edge trigger Octal D-type flip-flop; positive-edge trigger (3-state) Octal D-type flip-flop with data enable; positiveedge trigger Octal D-type flip-flop; positive-edge trigger (3-state) Dual D-type flip-flop with set and reset; positiveedge trigger 16-bit D-type flip-flop; positive-edge trigger (3-state) 16-bit D-type flip-flop with bus hold; positiveedge trigger (3-state) Dual JK-type flip-flop with set and reset; positive-edge trigger Single D flip-flop with reset; positive-edge trigger Single D-type flip-flop with set and reset; positive-edge trigger Logic switching levels Output drive capability (mA) t pd (ns) Output Load C L (Typ) f max (MHz) T amb (°C) 1.0 to 5.5 TTL ±12 16 50 pF 77 -40 to +125 1.0 to 5.5 TTL ±12 12 50 pF 110 -40 to +125 1.0 to 5.5 TTL ±16 14 50 pF 77 -40 to +125 1.0 to 3.6 TTL ±6 13 50 pF 77 -40 to +125 1.0 to 5.5 TTL ±16 13 50 pF 77 -40 to +125 1.0 to 5.5 TTL ±12 11 50 pF 75 -40 to +125 1.2 to 3.6 1.2 to 3.6 1.2 to 3.6 1.65 to 5.5 1.65 to 5.5 74LVC1G79 Single D-type flip-flop; positive-edge trigger 1.65 to 5.5 74LVC1G80 Single D-type flip-flop; positive-edge trigger 1.65 to 5.5 74LVC273 74LVC2G74 74LVC374 74LVC377 74LVC574 74LVC74 74LVC821 74LVC823 74LVCH162374 74LVCH32374 74LVT16374 74LVTH16374 Octal D-type flip-flop with reset; positive-edge trigger Single D-type flip-flop with set and reset; positive-edge trigger Octal D-type flip-flop; positive-edge trigger (3-state) Octal D-type flip-flop with data enable; positiveedge trigger Octal D-type flip-flop; positive-edge trigger (3-state) Dual D-type flip-flop with set and reset; positiveedge trigger 10-bit D-type flip-flop; positive-edge trigger (3-state) 9-bit D-type flip-flop; positive-edge trigger (3-state) 16-bit D-type flip-flop with bus hold and 30 Ω termination resistors; positive-edge trigger (3-state) 32-bit D-type flip-flop with bus hold; positiveedge trigger (3-state) 16-bit D-type flip-flop with bus hold; positiveedge trigger (3-state) 16-bit D-type flip-flop with bus hold; positiveedge trigger (3-state) 1.2 to 3.6 1.65 to 5.5 1.2 to 3.6 1.2 to 3.6 1.2 to 3.6 1.2 to 3.6 1.2 to 3.6 1.2 to 3.6 1.2 to 3.6 1.2 to 3.6 CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL ±24 3,8 50 pF 150 -40 to +125 ±24 3,8 50 pF 150 -40 to +125 ±24 4 50 pF 330 -40 to +125 ±32 3,1 50 pF 300 -40 to +125 ±32 3,5 50 pF 280 -40 to +125 ±32 2,2 50 pF 450 -40 to +125 ±32 2,4 50 pF 450 -40 to +125 ±24 6 50 pF 230 -40 to +125 ±32 3,5 50 pF 280 -40 to +125 ±24 2,7 50 pF 100 -40 to +125 ±24 6 50 pF 230 -40 to +125 ±24 3,2 50 pF 150 -40 to +125 ±24 2,5 50 pF 250 -40 to +125 ±24 5,4 50 pF 150 -40 to +125 ±24 5,4 50 pF 150 -40 to +125 ±24 3,8 50 pF 150 -40 to +125 ±24 3,8 50 pF 150 -40 to +125 2.7 to 3.6 TTL -32/+64 3 50 pF 150 -40 to +85 2.7 to 3.6 TTL -32/+64 3 50 pF 150 -40 to +85 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. NXP Logic selection guide 2016 85
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Logic selection guide 2016 Standard
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Standard Logic and Mini Logic: tune
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Transceivers 120 Standard logic pac
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NXP is the #1 volume leader For the
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What is configurable logic? Configu
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Our approach to quality At NXP, we
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Low-voltage families INCREASING PER
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Special features NXP offers a varie
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SOURCE TERMINATION What it does Imp
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OVERVOLTAGE-TOLERANT OUTPUTS 3-stat
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LIVE INSERTION What it does Enables
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OPEN-DRAIN OUTPUTS Open-drain outpu
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High-voltage families This section
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HEF4000B selection table (cont.) SO
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HC(T) selection table (cont.) TSSOP
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HC(T) selection table (cont.) TSSOP
Page 33 and 34: HC(T) selection table (cont.) TSSOP
Page 39 and 40: AHC(T) selection table (cont.) TSSO
Page 41 and 42: AHC(T) selection table (cont.) TSSO
Page 43 and 44: XC7 LOGIC XC7 devices are very high
Page 45 and 46: CBT(D) LOGIC CBT and CBTD bus switc
Page 47 and 48: LV selection table TSSOP SSOP SO DQ
Page 49 and 50: LVC selection table (cont.) TSSOP V
Page 55 and 56: ALVC selection table (cont.) TSSOP
Page 57 and 58: LVT selection table (cont.) TSSOP S
Page 59 and 60: AVC(M) LOGIC AVC and AVCM devices a
Page 61 and 62: AUP selection table (cont.) VSSOP M
Page 63 and 64: AXP LOGIC As the first logic family
Page 65 and 66: Product listing by function Analog
Page 67 and 68: Analog switches (cont.) Type number
Page 69 and 70: Buffers-inverters-drivers (cont.) T
Page 75 and 76: BUS SWITCHES Features and benefits
Page 77 and 78: Counters/frequency dividers (cont.)
Page 79 and 80: Decoders demultiplexers (cont.) Typ
Page 81 and 82: Digital multiplexers (cont.) Type n
Page 83: Flip-flops (cont.) Type number Desc
Page 87 and 88: GATES This section includes AND gat
Page 89 and 90: Gates - Configurable Type number De
Page 91 and 92: Gates - NAND (cont.) Type number De
Page 93 and 94: Gates - OR (cont.) Type number Desc
Page 95 and 96: Latches-registered drivers (cont.)
Page 97 and 98: Level shifters-translators (cont.)
Page 99 and 100: PARITY GENERATORS/CHECKERS Features
Page 101 and 102: Schmitt triggers (cont.) Type numbe
Page 103 and 104: Shift registers - LED drivers (cont
Page 105 and 106: Transceivers (cont.) Type number De
Page 107 and 108: Q100 Standard Logic functions & pac
Page 109 and 110: Buffers/inverters (cont.) Features
Page 111 and 112: Counters/frequency dividers (cont.)
Page 113 and 114: Flip-flops (cont.) Features Package
Page 115 and 116: Gates (cont.) Features Package (suf
Page 117 and 118: Level shifters/translators Features
Page 119 and 120: Shift registers (cont.) Features Pa
Page 121 and 122: Standard logic packages Package suf
Page 123 and 124: Buffers/inverters (cont.) Features
Page 125 and 126: Digital decoders/demultiplexers Fea
Page 127 and 128: Gates (cont.) Features Package (suf
Page 129 and 130: Level shifters/translators Features
Page 131 and 132: The leadless advantage Today’s ul
Page 133 and 134: Nomenclature NXP's naming conventio
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SOT457 GV SOT505-2 DP Pinout Pinout
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SOT765-1 DC SOT833-1 GT Pinout Pino
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SOT902-2 GM SOT996 GD Pinout Pinout
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SOT1089 GF SOT1202 GS Pinout Pinout
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SOT815-1 BQ SOT402-1 PW Pinout Pino
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SOT337-1 DB SOT338-1 DB Pinout Pino
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SOT724-1 DS SOT1174 GM Pinout Pinou
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SOT556-1 DK SOT340-1 DB Pinout Pino
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Design tools NXP is committed to ma
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Evaluation board for configurable l
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Toshiba one gate IDT logic TC7 S Z
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