Logic selection guide 2016

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Gates - OR (cont.) Type number Description V CC (V) HEF4072 HEF4075 XC7SET32 XC7SH32 Dual 4-input OR gate Triple 3-input OR gate Single 2-input OR gate; TTL-enabled Single 2-input OR gate Logic switching levels Output drive capability (mA) t pd (ns) Output Load C L (Typ) f max (MHz) Number of bits Power dissipation considerations T amb (°C) 4.5 to 15.5 CMOS ±2.4 25 50 pF 10 2 low -40 to +85 4.5 to 15.5 CMOS ±2.4 25 50 pF 10 3 low -40 to +85 4.5 to 5.5 TTL ±8 3.3 50 pF 60 1 low -40 to +125 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 1 low -40 to +125 LATCHES / REGISTERED DRIVERS Features and benefits 4 Improved synchronous operation, with reduced signal loads, elimination of timing delays and waveform distortion 4 Mixed 3.3/5 V applications 4 Reduced board space 4 Low-cost interface solutions 4 Improved signal integrity in complex layouts 4 Wide range of supply voltages 4 Low propagation delay 4 Low-power CMOS 4 Optional overvoltage-tolerant inputs, source termination, low input threshold Applications 4 Memory controllers 4 Backplane interfaces Latches-registered drivers (cont.) Type number Description V CC (V) Logic switching levels Output drive capability (mA) t pd (ns) Output Load C L (Typ) Number of bits T amb (°C) 74AHC259 8-bit addressable latch 2.0 to 5.5 CMOS ±8 4.1 50 pF 8 -40 to +125 74AHCT259 8-bit addressable latch; TTL-enabled 4.5 to 5.5 TTL ±8 4.1 50 pF 8 -40 to +125 74AHC373 Octal D-type transparent latch (3-state) 2.0 to 5.5 CMOS ±8 4.3 50 pF 8 -40 to +125 74AHCT373 Octal D-type transparent latch; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 4.3 50 pF 8 -40 to +125 74AHC573 Octal D-type transparent latch (3-state) 2.0 to 5.5 CMOS ±8 4.2 50 pF 8 -40 to +125 74AHCT573 74ALVC162334 74ALVC162834 74ALVC162835 74ALVC162836 Octal D-type transparent latch; TTL-enabled (3-state) 16-bit registered driver with 30 Ω termination resistors (3-state) 18-bit registered driver with 30 Ω termination resistors (3-state) 18-bit registered driver with 30 Ω termination resistors (3-state) 20-bit registered driver with 30 Ω termination resistors (3-state) 4.5 to 5.5 TTL ±8 3.9 50 pF 8 -40 to +125 1.65 to 3.6 LVTTL ±24 6 50 pF 16 -40 to +85 1.65 to 3.6 LVTTL ±24 6 50 pF 18 -40 to +85 1.65 to 3.6 LVTTL ±24 6 50 pF 18 -40 to +85 1.65 to 3.6 LVTTL ±24 6 50 pF 20 -40 to +85 74ALVC16834 18-bit registered driver (3-state) 1.65 to 3.6 LVTTL ±24 4 50 pF 18 -40 to +85 74ALVC16835 18-bit registered driver (3-state) 1.65 to 3.6 LVTTL ±24 4 50 pF 18 -40 to +85 74ALVC16836 20-bit registered driver (3-state) 1.65 to 3.6 LVTTL ±24 4 50 pF 20 -40 to +85 74ALVC373 Octal D-type transparent latch (3-state) 1.65 to 3.6 LVTTL ±24 2.2 50 pF 8 -40 to +85 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. 94 NXP Logic selection guide 2016
Latches-registered drivers (cont.) Type number Description V CC (V) Logic switching levels Output drive capability (mA) t pd (ns) Output Load C L (Typ) Number of bits T amb (°C) 74ALVC573 Octal D-type transparent latch (3-state) 1.65 to 3.6 LVTTL ±24 2.2 50 pF 8 -40 to +85 74ALVCH16373 74ALVCH16832 74ALVCH16841 74ALVCH16843 74ALVCH32973 74ALVT16260 74ALVT16373 16-bit D-type transparent latch with bus hold (3-state) 7-bit to 28-bit address register/driver (3-state) 20-bit D-type transparent latch with bus hold (3-state) 18-bit D-type transparent latch with bus hold (3-state) 16-bit transceiver and transparent D-type latch with 8 independent buffers 12-bit to 24-bit multiplexed D-type latch with bus hold (3-state) 16-bit D-type transparent latch with bus hold (3-state) 2.3 to 3.6 LVTTL ±24 2.1 50 pF 16 -40 to +85 2.3 to 3.6 LVTTL ±24 4 50 pF 7 -40 to +85 2.3 to 3.6 LVTTL ±24 2.4 50 pF 20 -40 to +85 2.3 to 3.6 LVTTL ±24 2.1 50 pF 18 -40 to +85 1.8 to 3.6 LVTTL ±24 2.5 50 pF 16 -40 to +85 2.3 to 3.6 TTL -32 / +64 2.8 50 pF 12 -40 to +85 2.3 to 3.6 TTL -32 / +64 1.8 50 pF 16 -40 to +85 74AUP1G373 Single D-type transparent latch (3-state) 1.1 to 3.6 CMOS 1.9 / -1.9 8.5 30 pF 1 -40 to +125 74AVC16334 16-bit registered driver (3-state) 1.2 to 3.6 CMOS ±12 2 30 pF 16 -40 to +85 74AVC16373 16-bit D-type transparent latch (3-state) 1.2 to 3.6 CMOS ±12 2 30 pF 16 -40 to +85 74AVC16834 18-bit registered driver (3-state) 1.2 to 3.6 CMOS ±12 2 30 pF 18 -40 to +85 74AVC16835 18-bit registered driver (3-state) 1.2 to 3.6 CMOS ±12 2 30 pF 18 -40 to +85 74AVC16836 20-bit registered driver (3-state) 1.2 to 3.6 CMOS ±12 2 30 pF 20 -40 to +85 74AVCM162834 74AVCM162835 74AVCM162836 18-bit registered driver with 30 Ω termination resistors (3-state) 18-bit registered driver with 15 Ω termination resistors (3-state) 20-bit registered driver with 15 Ω termination resistors (3-state) 1.2 to 3.6 CMOS ±12 2 30 pF 18 -40 to +85 1.2 to 3.6 CMOS ±12 2 30 pF 18 -40 to +85 1.2 to 3.6 CMOS ±12 2 30 pF 20 -40 to +85 74HC259 8-bit addressable latch 2.0 to 6.0 CMOS ±5.2 18 50 pF 8 -40 to +125 74HCT259 8-bit addressable latch; TTL-enabled 4.5 to 5.5 TTL ±4 20 50 pF 8 -40 to +125 74HC373 Octal D-type transparent latch (3-state) 2.0 to 6.0 CMOS ±7.8 12 50 pF 8 -40 to +125 74HCT373 74HCT563 Octal D-type transparent latch; TTL-enabled (3-state) Octal D-type transparent latch; inverting; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 14 50 pF 8 -40 to +125 4.5 to 5.5 TTL ±6 16 50 pF 8 -40 to +125 74HC573 Octal D-type transparent latch (3-state) 2.0 to 6.0 CMOS ±7.8 14 50 pF 8 -40 to +125 74HCT573 Octal D-type transparent latch; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 17 50 pF 8 -40 to +125 74HC670 4-bit x 4-word register (3-state) 2.0 to 6.0 CMOS ±7.8 17 50 pF 4 -40 to +125 74HCT670 4-bit x 4-word register; TTL-enabled (3-state) 4.5 to 5.5 TTL ±6 23 50 pF 4 -40 to +125 74HC75 Quad bistable transparent latch 2.0 to 6.0 CMOS ±5.2 11 50 pF 4 -40 to +125 74HC75 Quad bistable transparent latch 2.0 to 6.0 CMOS ±5.2 11 50 pF 4 -40 to +125 74LV259 8-bit addressable latch 1.0 to 3.6 CMOS ±6 17 50 pF 8 -40 to +125 74LV373 Octal D-type transparent latch (3-state) 1.0 to 5.5 CMOS ±16 10 50 pF 8 -40 to +125 74LV573 Octal D-type transparent latch (3-state) 1.0 to 5.5 CMOS ±16 12 50 pF 8 -40 to +125 74LVC162373 74LVCH162373 16-bit D-type transparent latch with 30 Ω termination resistors (3-state) 16-bit D-type transparent latch with bus hold and 30 Ω termination resistors (3-state) 1.2 to 3.6 TTL ±12 3.2 50 pF 16 -40 to +125 1.2 to 3.6 TTL ±24 3.2 50 pF 16 -40 to +125 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. NXP Logic selection guide 2016 95
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Logic selection guide 2016 Standard
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Standard Logic and Mini Logic: tune
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Transceivers 120 Standard logic pac
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NXP is the #1 volume leader For the
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What is configurable logic? Configu
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Our approach to quality At NXP, we
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Low-voltage families INCREASING PER
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Special features NXP offers a varie
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SOURCE TERMINATION What it does Imp
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OVERVOLTAGE-TOLERANT OUTPUTS 3-stat
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LIVE INSERTION What it does Enables
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OPEN-DRAIN OUTPUTS Open-drain outpu
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High-voltage families This section
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HEF4000B selection table (cont.) SO
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HC(T) selection table (cont.) TSSOP
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AHC(T) selection table (cont.) TSSO
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AHC(T) selection table (cont.) TSSO
Page 43 and 44: XC7 LOGIC XC7 devices are very high
Page 45 and 46: CBT(D) LOGIC CBT and CBTD bus switc
Page 47 and 48: LV selection table TSSOP SSOP SO DQ
Page 49 and 50: LVC selection table (cont.) TSSOP V
Page 55 and 56: ALVC selection table (cont.) TSSOP
Page 57 and 58: LVT selection table (cont.) TSSOP S
Page 59 and 60: AVC(M) LOGIC AVC and AVCM devices a
Page 61 and 62: AUP selection table (cont.) VSSOP M
Page 63 and 64: AXP LOGIC As the first logic family
Page 65 and 66: Product listing by function Analog
Page 67 and 68: Analog switches (cont.) Type number
Page 69 and 70: Buffers-inverters-drivers (cont.) T
Page 75 and 76: BUS SWITCHES Features and benefits
Page 77 and 78: Counters/frequency dividers (cont.)
Page 79 and 80: Decoders demultiplexers (cont.) Typ
Page 81 and 82: Digital multiplexers (cont.) Type n
Page 83 and 84: Flip-flops (cont.) Type number Desc
Page 85 and 86: Flip-flops (cont.) Type number Desc
Page 87 and 88: GATES This section includes AND gat
Page 89 and 90: Gates - Configurable Type number De
Page 91 and 92: Gates - NAND (cont.) Type number De
Page 93: Gates - OR (cont.) Type number Desc
Page 97 and 98: Level shifters-translators (cont.)
Page 99 and 100: PARITY GENERATORS/CHECKERS Features
Page 101 and 102: Schmitt triggers (cont.) Type numbe
Page 103 and 104: Shift registers - LED drivers (cont
Page 105 and 106: Transceivers (cont.) Type number De
Page 107 and 108: Q100 Standard Logic functions & pac
Page 109 and 110: Buffers/inverters (cont.) Features
Page 111 and 112: Counters/frequency dividers (cont.)
Page 113 and 114: Flip-flops (cont.) Features Package
Page 115 and 116: Gates (cont.) Features Package (suf
Page 117 and 118: Level shifters/translators Features
Page 119 and 120: Shift registers (cont.) Features Pa
Page 121 and 122: Standard logic packages Package suf
Page 123 and 124: Buffers/inverters (cont.) Features
Page 125 and 126: Digital decoders/demultiplexers Fea
Page 127 and 128: Gates (cont.) Features Package (suf
Page 129 and 130: Level shifters/translators Features
Page 131 and 132: The leadless advantage Today’s ul
Page 133 and 134: Nomenclature NXP's naming conventio
Page 135 and 136: SOT457 GV SOT505-2 DP Pinout Pinout
Page 137 and 138: SOT765-1 DC SOT833-1 GT Pinout Pino
Page 139 and 140: SOT902-2 GM SOT996 GD Pinout Pinout
Page 141 and 142: SOT1089 GF SOT1202 GS Pinout Pinout
Page 143 and 144: SOT815-1 BQ SOT402-1 PW Pinout Pino
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SOT337-1 DB SOT338-1 DB Pinout Pino
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SOT724-1 DS SOT1174 GM Pinout Pinou
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SOT556-1 DK SOT340-1 DB Pinout Pino
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Design tools NXP is committed to ma
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Evaluation board for configurable l
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Toshiba one gate IDT logic TC7 S Z
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