Logic selection guide 2016

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Q100 Mini Logic functions & packages Mini logic functions are small footprint logic devices with 10 pins or less suitable for use at supply voltage between 1.1 V to 6.0 V. They provide a wide range of functions including analog switches, buffers/inverters, bus switches, decoders/demultiplexers, multiplexers, flip-flops, gates, configurable logic and level shifters. Q100 Mini logic functions are available in leaded TSSOP and VSSOP packages as well as innovative leadless XSON packages. Analog switches Features Package (suffix) Type number Description Configuration V CC (V) R ON (W) R ON (FLAT) (W) T amb (°C) SOT353-1 (GW) SOT753 (GV) SOT363 (GW) SOT457 (GV) SOT505-2 (DP) SOT765-1 (DC) 74AHC1G66-Q100 Single-pole, single-throw analog switch SPST-NO 2.0 - 5.5 40 5 -40~125 • • 74AHCT1G66-Q100 Single-pole, single-throw analog switch; TTL-enabled SPST-NO 4.5 - 5.5 40 5 -40~125 • • 74HC1G66-Q100 Single-pole, single-throw analog switch SPST-NO 2.0 - 9.0 105 23 -40~125 • • 74HCT1G66-Q100 Single-pole, single-throw analog switch; TTL-enabled SPST-NO 4.5 - 5.5 118 23 -40~125 • • 74HC2G66-Q100 Dual single-pole, single-throw analog switch SPST-NO 2.0 - 9.0 105 23 -40~125 • • 74HCT2G66-Q100 Dual single-pole, single-throw analog switch; TTL-enabled SPST-NO 4.5 - 5.5 118 23 -40~125 • • 74LVC1G53-Q100 Single-pole, double-throw analog switch SPDT-Z 1.65 - 5.5 15 1.5 -40~125 • • 74LVC1G66-Q100 Single-pole, single-throw analog switch SPST-NO 1.65 - 5.5 15 1.5 -40~125 • • 74LVC1G384-Q100 Single-pole, single-throw analog switch SPST-NC 1.65 - 5.5 15 1.5 -40~125 • • 74LVC1G3157-Q100 Single-pole, double-throw analog switch SPDT 1.65 - 5.5 15 1.5 -40~125 • • 74LVC2G66-Q100 Dual single-pole, single-throw analog switch SPST-NO 1.65 - 5.5 15 1.5 -40~125 • • Bus switches Features Package (suffix) Type number Description V CC (V) V PASS (V) R ON (W) T amb (°C) SOT96-1 (D) SOT530-1 (PW) CBT3306-Q100 Dual bus switch 4.5 - 5.5 3.9 7 -40~85 • • 122 NXP Logic selection guide 2016
Buffers/inverters (cont.) Features Package (suffix) Type number Description V CC (V) I O (mA) t pd (ns) T amb (°C) SOT353-1 (GW) SOT753 (GV) SOT363 (GW) SOT457 (GV) SOT505-2 (DP) SOT765-1 (DC) SOT996-2 (GD) 74AHC1GU04-Q100 Single inverter; unbuffered 2.0 - 5.5 ± 8 2.6 -40~125 • • 74AHC3GU04-Q100 Triple inverter; unbuffered 2.0 - 5.5 ± 8 2.5 -40~125 • • 74AHC1G04-Q100 Single inverter 2.0 - 5.5 ± 8 3.1 -40~125 • • 74AHCT1G04-Q100 Single inverter; TTL-enabled 4.5 - 5.5 ± 8 3.4 -40~125 • • 74AHC1G07-Q100 Single buffer; open-drain 2.0 - 5.5 8 4.2 -40~125 • • 74AHC1G125-Q100 Single buffer/line driver (3-state) 2.0 - 5.5 ± 8 3.4 -40~125 • • 74AHCT1G125-Q100 Single buffer/line driver; TTL-enabled (3-state) 4.5 - 5.5 ± 8 3.4 -40~125 • • 74AHC1G126-Q100 Single buffer/line driver (3-state) 2.0 - 5.5 ± 8 3.4 -40~125 • • 74AHCT1G126-Q100 Single buffer/line driver; TTL-enabled (3-state) 4.5 - 5.5 ± 8 3.4 -40~125 • • 74AHC2G125-Q100 Dual buffer/line driver (3-state) 2.0 - 5.5 ± 8 3.4 -40~125 • • 74AHCT2G125-Q100 Dual buffer/line driver; TTL-enabled (3-state) 4.5 - 5.5 ± 8 3.4 -40~125 • • 74AHC2G126-Q100 Dual buffer/line driver (3-state) 2.0 - 5.5 ± 8 3.4 -40~125 • • 74AHCT2G126-Q100 Dual buffer/line driver; TTL-enabled (3-state) 4.5 - 5.5 ± 8 3.4 -40~125 • • 74AHC2G241-Q100 Dual buffer/line driver (3-state) 2.0 - 5.5 ± 8 3.4 -40~125 • • 74AHCT2G241-Q100 Dual buffer/line driver; TTL-enabled (3-state) 4.5 - 5.5 ± 8 3.4 -40~125 • • 74AHC3G04-Q100 Triple inverter 2.0 - 5.5 ± 8 3.1 -40~125 • • 74AHCT3G04-Q100 Triple inverter; TTL-enabled 4.5 - 5.5 ± 8 3 -40~125 • • 74AUP1G04-Q100 Single inverter 1.1 - 3.6 ± 1.9 4 -40~125 • • 74AUP1G06-Q100 Single inverter; open-drain 1.1 - 3.6 1.9 4.5 -40~125 • 74AUP1G34-Q100 Single buffer 1.1 - 3.6 ± 1.9 3.9 -40~125 • 74AUP1G125-Q100 Single buffer/line driver (3-state) 1.1 - 3.6 ± 1.9 4.3 -40~125 • 74AUP2GU04-Q100 Dual inverter; unbuffered 1.1 - 3.6 ± 1.9 2.3 -40~125 • 74HC1GU04-Q100 Single inverter; unbuffered 2.0 - 6.0 ± 2.6 5 -40~125 • • 74HC2GU04-Q100 Dual inverter; unbuffered 2.0 - 6.0 ± 5.2 5 -40~125 • • 74HC3GU04-Q100 Triple inverter; unbuffered 2.0 - 6.0 ± 5.2 6 -40~125 • • 74HC1G04-Q100 Single inverter 2.0 - 6.0 ± 2.6 7 -40~125 • • 74HCT1G04-Q100 Single inverter; TTL-enabled 4.5 - 5.5 ± 2.0 8 -40~125 • • 74HC1G125-Q100 Single buffer/line driver (3-state) 2.0 - 6.0 ± 2.6 9 -40~125 • • 74HCT1G125-Q100 Single buffer/line driver; TTL-enabled (3-state) 4.5 - 5.5 ± 2.0 10 -40~125 • • 74HC2G04-Q100 Dual inverter 2.0 - 6.0 ± 5.2 8 -40~125 • • 74HCT2G04-Q100 Dual inverter; TTL-enabled 4.5 - 5.5 ± 4.0 10 -40~125 • • 74HC2G34-Q100 Dual buffer 2.0 - 6.0 ± 5.2 9 -40~125 • • 74HCT2G34-Q100 Dual buffer; TTL-enabled 4.5 - 5.5 ± 4.0 10 -40~125 • • 74HC2G125-Q100 Dual buffer/line driver (3-state) 2.0 - 6.0 ± 5.2 10 -40~125 • • NXP Logic selection guide 2016 123
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Logic selection guide 2016 Standard
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Standard Logic and Mini Logic: tune
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Transceivers 120 Standard logic pac
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NXP is the #1 volume leader For the
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What is configurable logic? Configu
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Our approach to quality At NXP, we
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Low-voltage families INCREASING PER
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Special features NXP offers a varie
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SOURCE TERMINATION What it does Imp
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OVERVOLTAGE-TOLERANT OUTPUTS 3-stat
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LIVE INSERTION What it does Enables
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OPEN-DRAIN OUTPUTS Open-drain outpu
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High-voltage families This section
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HEF4000B selection table (cont.) SO
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HC(T) selection table (cont.) TSSOP
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AHC(T) selection table (cont.) TSSO
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AHC(T) selection table (cont.) TSSO
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XC7 LOGIC XC7 devices are very high
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CBT(D) LOGIC CBT and CBTD bus switc
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LV selection table TSSOP SSOP SO DQ
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LVC selection table (cont.) TSSOP V
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ALVC selection table (cont.) TSSOP
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LVT selection table (cont.) TSSOP S
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AVC(M) LOGIC AVC and AVCM devices a
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AUP selection table (cont.) VSSOP M
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AXP LOGIC As the first logic family
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Product listing by function Analog
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Analog switches (cont.) Type number
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Buffers-inverters-drivers (cont.) T
Page 71 and 72: Buffers-inverters-drivers (cont.) T
Page 73 and 74: Buffers-inverters-drivers (cont.) T
Page 75 and 76: BUS SWITCHES Features and benefits
Page 77 and 78: Counters/frequency dividers (cont.)
Page 79 and 80: Decoders demultiplexers (cont.) Typ
Page 81 and 82: Digital multiplexers (cont.) Type n
Page 83 and 84: Flip-flops (cont.) Type number Desc
Page 85 and 86: Flip-flops (cont.) Type number Desc
Page 87 and 88: GATES This section includes AND gat
Page 89 and 90: Gates - Configurable Type number De
Page 91 and 92: Gates - NAND (cont.) Type number De
Page 93 and 94: Gates - OR (cont.) Type number Desc
Page 95 and 96: Latches-registered drivers (cont.)
Page 97 and 98: Level shifters-translators (cont.)
Page 99 and 100: PARITY GENERATORS/CHECKERS Features
Page 101 and 102: Schmitt triggers (cont.) Type numbe
Page 103 and 104: Shift registers - LED drivers (cont
Page 105 and 106: Transceivers (cont.) Type number De
Page 107 and 108: Q100 Standard Logic functions & pac
Page 109 and 110: Buffers/inverters (cont.) Features
Page 111 and 112: Counters/frequency dividers (cont.)
Page 113 and 114: Flip-flops (cont.) Features Package
Page 115 and 116: Gates (cont.) Features Package (suf
Page 117 and 118: Level shifters/translators Features
Page 119 and 120: Shift registers (cont.) Features Pa
Page 121: Standard logic packages Package suf
Page 125 and 126: Digital decoders/demultiplexers Fea
Page 127 and 128: Gates (cont.) Features Package (suf
Page 129 and 130: Level shifters/translators Features
Page 131 and 132: The leadless advantage Today’s ul
Page 133 and 134: Nomenclature NXP's naming conventio
Page 135 and 136: SOT457 GV SOT505-2 DP Pinout Pinout
Page 137 and 138: SOT765-1 DC SOT833-1 GT Pinout Pino
Page 139 and 140: SOT902-2 GM SOT996 GD Pinout Pinout
Page 141 and 142: SOT1089 GF SOT1202 GS Pinout Pinout
Page 143 and 144: SOT815-1 BQ SOT402-1 PW Pinout Pino
Page 145 and 146: SOT337-1 DB SOT338-1 DB Pinout Pino
Page 147 and 148: SOT724-1 DS SOT1174 GM Pinout Pinou
Page 149 and 150: SOT556-1 DK SOT340-1 DB Pinout Pino
Page 151 and 152: Design tools NXP is committed to ma
Page 153 and 154: Evaluation board for configurable l
Page 155 and 156: Toshiba one gate IDT logic TC7 S Z
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