Logic selection guide 2016

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Gates - EXCLUSIVE-OR (cont.) Type number Description V CC (V) 74HCT1G86 Single 2-input EXCLUSIVE-OR gate; TTL-enabled Logic switching levels Output drive capability (mA) t pd (ns) Output Load C L (Typ) f max (MHz) Number of bits T amb (°C) 4.5 to 5.5 TTL ±2.0 10 50 pF 36 1 -40 to +125 74HC2G86 Dual 2-input EXCLUSIVE-OR gate 2.0 to 6.0 CMOS ±5.2 9 50 pF 36 2 -40 to +125 74HCT2G86 Dual 2-input EXCLUSIVE-OR gate; TTL-enabled 4.5 to 5.5 TTL ±4.0 11 50 pF 36 2 -40 to +125 74HC86 Quad 2-input EXCLUSIVE-OR gate 2.0 to 6.0 CMOS ±5.2 11 50 pF 36 4 -40 to +125 74HCT86 Quad 2-input EXCLUSIVE-OR gate; TTL-enabled 4.5 to 5.5 TTL ±4 14 50 pF 36 4 -40 to +125 74LV86 Quad 2-input EXCLUSIVE-OR gate 1.0 to 5.5 TTL ±12 11 50 pF 30 4 -40 to +125 74LVC1G386 Single 3-Input EXCLUSIVE-OR gate 1.65 to 5.5 74LVC1G86 Single 2-input EXCLUSIVE-OR gate 1.65 to 5.5 74LVC2G86 Dual 2-input EXCLUSIVE-OR gate 1.65 to 5.5 74LVC86 Quad 2-input EXCLUSIVE-OR gate 1.2 to 3.6 CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL ±32 4.5 50 pF 150 1 -40 to +125 ±32 2.4 50 pF 150 1 -40 to +125 ±32 2.3 50 pF 150 2 -40 to +125 ±24 3 50 pF 150 4 -40 to +125 HEF4030 Quad 2-input EXCLUSIVE-OR gate 4.5 to 15.5 CMOS ±2.4 30 50 pF 10 4 -40 to +85 HEF4070 Quad 2-input EXCLUSIVE-OR gate 4.5 to 15.5 CMOS ±2.4 30 50 pF 10 4 -40 to +85 XC7SET86 2-input EXCLUSIVE-OR gate; TTL-enabled 4.5 to 5.5 TTL ±8 3.5 50 pF 60 1 -40 to +125 XC7SH86 2-input EXCLUSIVE-OR gate 2.0 to 5.5 CMOS ±8 3,4 50 pF 60 1 -40 to +125 Gates - NAND (cont.) Type number Description V CC (V) Logic switching levels Output drive capability (mA) t pd (ns) Output Load C L (Typ) f max (MHz) Number of bits T amb (°C) 74AHC00 Quad 2-input NAND gate 2.0 to 5.5 CMOS ±8 3.2 50 pF 60 4 -40 to +125 74AHCT00 Quad 2-input NAND gate; TTL-enabled 4.5 to 5.5 TTL ±8 3.3 50 pF 60 4 -40 to +125 74AHC1G00 Single 2-input NAND gate 2.0 to 5.5 CMOS ±8 3.5 50 pF 60 1 -40 to +125 74AHCT1G00 Single 2-input NAND gate; TTL-enabled 4.5 to 5.5 TTL ±8 3.6 50 pF 60 1 -40 to +125 74AHC2G00 Dual 2-input NAND gate 2.0 to 5.5 CMOS ±8 3.5 50 pF 60 2 -40 to +125 74AHCT2G00 Dual 2-input NAND gate; TTL-enabled 4.5 to 5.5 TTL ±8 3.6 50 pF 60 2 -40 to +125 74AHC30 8-input NAND gate 2.0 to 5.5 CMOS ±8 3.6 50 pF 60 1 -40 to +125 74AHCT30 8-input NAND gate; TTL-enabled 4.5 to 5.5 TTL ±8 3.3 50 pF 60 1 -40 to +125 74ALVC00 Quad 2-input NAND gate 1.65-3.6 TTL ±24 2.1 50 pF 145 4 -40 to +85 74AUP1G00 Single 2-input NAND gate 1.1 to 3.6 CMOS 1.9/-1.9 8.3 30 pF 70 1 -40 to +125 74AUP1G132 74AUP1G38 Single 2-input NAND gate Schmitt trigger Single 2-input NAND gate; open drain 1.1 to 3.6 CMOS 1.9/-1.9 10 30 pF 70 1 -40 to +125 1.1 to 3.6 CMOS 1,9 8.5 30 pF 70 1 -40 to +125 74AUP2G00 Dual 2-input NAND gate 1.1 to 3.6 CMOS 1.9/-1.9 8.3 30 pF 70 2 -40 to +125 74AUP2G38 Dual 2-input NAND gate; open drain 1.1 to 3.6 CMOS 1,9 8.5 30 pF 70 2 -40 to +125 74HC00 Quad 2-input NAND gate 2.0 to 6.0 CMOS ±5.2 7 50 pF 36 4 -40 to +125 74HCT00 Quad 2-input NAND gate; TTL-enabled 4.5 to 5.5 TTL ±4 10 50 pF 36 4 -40 to +125 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. 90 NXP Logic selection guide 2016
Gates - NAND (cont.) Type number Description V CC (V) 74HC03 74HCT03 Quad 2-input NAND gate; open drain Quad 2-input NAND gate; open drain; TTL-enabled Logic switching levels Output drive capability (mA) t pd (ns) Output Load C L (Typ) f max (MHz) Number of bits T amb (°C) 2.0 to 6.0 CMOS 5,2 8 50 pF 36 4 -40 to +125 4.5 to 5.5 TTL ±4 10 50 pF 36 4 -40 to +125 74HC10 Triple 3-input NAND gate 2.0 to 6.0 CMOS ±5.2 9 50 pF 36 3 -40 to +125 74HCT10 Triple 3-input NAND gate; TTL-enabled 4.5 to 5.5 TTL ±4 11 50 pF 36 3 -40 to +125 74HC1G00 Single 2-input NAND gate 2.0 to 6.0 CMOS ±2.6 7 50 pF 36 1 -40 to +125 74HCT1G00 Single 2-input NAND gate; TTL-enabled 4.5 to 5.5 TTL ±2 10 50 pF 36 1 -40 to +125 74HC20 Dual 4-input NAND gate 2.0 to 6.0 CMOS ±5.2 8 50 pF 36 2 -40 to +125 74HCT20 Dual 4-input NAND gate; TTL-enabled 4.5 to 5.5 TTL ±4 13 50 pF 36 2 -40 to +125 74HC2G00 Dual 2-input NAND gate 2.0 to 6.0 CMOS ±5.6 9 50 pF 36 2 -40 to +125 74HCT2G00 Dual 2-input NAND gate; TTL-enabled 4.5 to 5.5 TTL ±4 12 50 pF 36 2 -40 to +125 74HC30 8-input NAND gate 2.0 to 6.0 CMOS ±5.2 12 50 pF 36 1 -40 to +125 74HCT30 8-input NAND gate; TTL-enabled 4.5 to 5.5 TTL ±4 12 50 pF 36 1 -40 to +125 74LV00 Quad 2-input NAND gate 1.0 to 5.5 TTL ±12 7 50 pF 30 4 -40 to +125 74LV03 Quad 2-input NAND gate; open drain 74LVC00 Quad 2-input NAND gate 1.2 to 3.6 74LVC10 Triple 3-input NAND gate 1.2 to 3.6 74LVC1G00 Single 2-input NAND gate 1.65 to 5.5 74LVC1G10 Single 3-input NAND gate 1.65 to 5.5 74LVC1G38 Single 2-input NAND gate; open drain 1.0 to 5.5 TTL ±12 8 50 pF 30 4 -40 to +125 1.65 to 5.5 74LVC2G00 Dual 2-input NAND gate 1.65 to 5.5 74LVC2G38 Dual 2-input NAND gate; open drain 1.65 to 5.5 74LVC30 8-input NAND gate 1.65 to 5.6 74LVC38 Quad 2-input NAND gate; open drain 1.2 to 3.6 CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL CMOS/ LVTTL ±24 2.1 50 pF 150 4 -40 to +125 ±24 3.9 50 pF 150 3 -40 to +125 ±32 2.2 50 pF 175 1 -40 to +125 ±32 2.6 50 pF 175 1 -40 to +125 32 2.3 50 pF 175 1 -40 to +125 ±32 2.2 50 pF 175 2 -40 to +125 32 2.1 50 pF 175 2 -40 to +125 24 3.6 50 pF 175 1 -40 to +125 24 2.2 50 pF 175 4 -40 to +125 74LVT00 Quad 2-input NAND gate 2.7 to 3.6 TTL -32/+64 2.7 50 pF 150 4 -40 to +85 74LVT10 Triple 3-input NAND gate 2.7 to 3.6 TTL -32/+64 3.8 50 pF 150 3 -40 to +85 HEF4011 Quad 2-input NAND gate 4.5 to 15.5 CMOS ±2.4 20 50 pF 10 4 -40 to +85 HEF4023 Triple 3-input NAND gate 4.5 to 15.5 CMOS ±2.4 25 50 pF 10 3 -40 to +85 HEF4068 8-input NAND gate 4.5 to 15.5 CMOS ±2.4 30 50 pF 10 1 -40 to +85 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. NXP Logic selection guide 2016 91
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Logic selection guide 2016 Standard
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Standard Logic and Mini Logic: tune
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Transceivers 120 Standard logic pac
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NXP is the #1 volume leader For the
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What is configurable logic? Configu
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Our approach to quality At NXP, we
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Low-voltage families INCREASING PER
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Special features NXP offers a varie
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SOURCE TERMINATION What it does Imp
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OVERVOLTAGE-TOLERANT OUTPUTS 3-stat
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LIVE INSERTION What it does Enables
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OPEN-DRAIN OUTPUTS Open-drain outpu
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High-voltage families This section
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HEF4000B selection table (cont.) SO
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HC(T) selection table (cont.) TSSOP
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Page 39 and 40: AHC(T) selection table (cont.) TSSO
Page 41 and 42: AHC(T) selection table (cont.) TSSO
Page 43 and 44: XC7 LOGIC XC7 devices are very high
Page 45 and 46: CBT(D) LOGIC CBT and CBTD bus switc
Page 47 and 48: LV selection table TSSOP SSOP SO DQ
Page 49 and 50: LVC selection table (cont.) TSSOP V
Page 55 and 56: ALVC selection table (cont.) TSSOP
Page 57 and 58: LVT selection table (cont.) TSSOP S
Page 59 and 60: AVC(M) LOGIC AVC and AVCM devices a
Page 61 and 62: AUP selection table (cont.) VSSOP M
Page 63 and 64: AXP LOGIC As the first logic family
Page 65 and 66: Product listing by function Analog
Page 67 and 68: Analog switches (cont.) Type number
Page 69 and 70: Buffers-inverters-drivers (cont.) T
Page 75 and 76: BUS SWITCHES Features and benefits
Page 77 and 78: Counters/frequency dividers (cont.)
Page 79 and 80: Decoders demultiplexers (cont.) Typ
Page 81 and 82: Digital multiplexers (cont.) Type n
Page 83 and 84: Flip-flops (cont.) Type number Desc
Page 85 and 86: Flip-flops (cont.) Type number Desc
Page 87 and 88: GATES This section includes AND gat
Page 89: Gates - Configurable Type number De
Page 93 and 94: Gates - OR (cont.) Type number Desc
Page 95 and 96: Latches-registered drivers (cont.)
Page 97 and 98: Level shifters-translators (cont.)
Page 99 and 100: PARITY GENERATORS/CHECKERS Features
Page 101 and 102: Schmitt triggers (cont.) Type numbe
Page 103 and 104: Shift registers - LED drivers (cont
Page 105 and 106: Transceivers (cont.) Type number De
Page 107 and 108: Q100 Standard Logic functions & pac
Page 109 and 110: Buffers/inverters (cont.) Features
Page 111 and 112: Counters/frequency dividers (cont.)
Page 113 and 114: Flip-flops (cont.) Features Package
Page 115 and 116: Gates (cont.) Features Package (suf
Page 117 and 118: Level shifters/translators Features
Page 119 and 120: Shift registers (cont.) Features Pa
Page 121 and 122: Standard logic packages Package suf
Page 123 and 124: Buffers/inverters (cont.) Features
Page 125 and 126: Digital decoders/demultiplexers Fea
Page 127 and 128: Gates (cont.) Features Package (suf
Page 129 and 130: Level shifters/translators Features
Page 131 and 132: The leadless advantage Today’s ul
Page 133 and 134: Nomenclature NXP's naming conventio
Page 135 and 136: SOT457 GV SOT505-2 DP Pinout Pinout
Page 137 and 138: SOT765-1 DC SOT833-1 GT Pinout Pino
Page 139 and 140: SOT902-2 GM SOT996 GD Pinout Pinout
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SOT1089 GF SOT1202 GS Pinout Pinout
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SOT815-1 BQ SOT402-1 PW Pinout Pino
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SOT337-1 DB SOT338-1 DB Pinout Pino
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SOT724-1 DS SOT1174 GM Pinout Pinou
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SOT556-1 DK SOT340-1 DB Pinout Pino
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Design tools NXP is committed to ma
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Evaluation board for configurable l
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Toshiba one gate IDT logic TC7 S Z
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