Logic selection guide 2016

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DECODERS/DEMULTIPLEXERS Features and benefits 4 Multiple input enable for easy expansion, independent controls 4 Integrated input latch for storing decoder-line addresses 4 Asynchronous and synchronous load options 4 Can be cascaded 4 High frequency 4 Bus-width reduction 4 Optional overvoltage-tolerant inputs, inverting and noninverting outputs, and 3-stage outputs Applications 4 Selection of memory banks and peripherals 4 I/O expansion 4 Memory addressing in automotive (display clusters, GPS, keyless entry) Decoders demultiplexers (cont.) Type number Description V CC (V) Logic switching levels Output drive capability (mA) t pd (ns) Output Load C L (Typ) T amb (°C) 74AHC138 3-to-8 line decoder/demultiplexer; inverting 2.0 to 5.5 CMOS ±8 4.4 50 pF -40 to +125 74AHCT138 3-to-8 line decoder/demultiplexer; inverting; TTL-enabled 4.5 to 5.5 TTL ±8 4.4 50 pF -40 to +125 74AHC139 Dual 2-to-4 line decoder/demultiplexer 2.0 to 5.5 CMOS ±8 3.9 50 pF -40 to +125 74AHCT139 Dual 2-to-4 line decoder/demultiplexer; TTL-enabled 4.5 to 5.5 TTL ±8 3.6 50 pF -40 to +125 74AUP1G18 1-to-2 demultiplexer (3-state) 1.1 to 3.6 CMOS 1.9/-1.9 3.2 30 pF -40 to +125 74AUP1G19 1-to-2 decoder/demultiplexer 1.1 to 3.6 CMOS 1.9/-1.9 3 30 pF -40 to +125 74HC138 3-to-8 line decoder/demultiplexer; inverting 2.0 to 6.0 CMOS ±5.2 12 50 pF -40 to +125 74HCT138 3-to-8 line decoder/demultiplexer; inverting; TTL-enabled 4.5 to 5.5 TTL ±4 19 50 pF -40 to +125 74HC139 Dual 2-to-4 line decoder/demultiplexer 2.0 to 6.0 CMOS ±5.2 14 50 pF -40 to +125 74HCT139 Dual 2-to-4 line decoder/demultiplexer; TTL-enabled 4.5 to 5.5 TTL ±4 16 50 pF -40 to +125 74HC154 4-to-16 line decoder/demultiplexer 2.0 to 6.0 CMOS ±5.2 11 50 pF -40 to +125 74HCT154 4-to-16 line decoder/demultiplexer; TTL-enabled 4.5 to 5.5 TTL ±4 13 50 pF -40 to +125 74HC238 3-to-8 decoder/demultiplexer 2.0 to 6.0 CMOS ±5.2 14 50 pF -40 to +125 74HCT238 3-to-8 decoder/demultiplexer; TTL-enabled 4.5 to 5.5 TTL ±4 18 50 pF -40 to +125 74HC42 BCD to decimal decoder (1-of-10) 2.0 to 6.0 CMOS ±5.2 17 50 pF -40 to +125 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. 78 NXP Logic selection guide 2016
Decoders demultiplexers (cont.) Type number Description V CC (V) Logic switching levels Output drive capability (mA) t pd (ns) Output Load C L (Typ) T amb (°C) 74HCT42 BCD to decimal decoder (1-of-10); TTL-enabled 4.5 to 5.5 TTL ±4 20 50 pF -40 to +125 74HC4511 74HCT4511 BCD to 7-segment latch/decoder/driver with lamp test input BCD to 7-segment latch/decoder/driver with lamp test input; TTL-enabled 2.0 to 6.0 CMOS -10 28 50 pF -40 to +125 4.5 to 5.5 TTL -10 28 50 pF -40 to +125 74HC4514 4-to-16 decoder/demultiplexer with address latches 2.0 to 6.0 CMOS ±5.2 27 50 pF -40 to +125 74HCT4514 74HC4515 74HCT4515 74HC137 4-to-16 decoder/demultiplexer with address latches; TTL-enabled 4-to-16 decoder/demultiplexer with address latches; inverting 4-to-16 decoder/demultiplexer with address latches; inverting; TTL-enabled 3-to-8 line decoder/demultiplexer with address latches; inverting 4.5 to 5.5 TTL ±4 30 50 pF -40 to +125 2.0 to 6.0 CMOS ±5.2 29 50 pF -40 to +125 4.5 to 5.5 TTL ±4 30 50 pF -40 to +125 2.0 to 6.0 CMOS ±5.2 18 50 pF -40 to +125 74HC237 3-to-8 decoder/demultiplexer with address latches 2.0 to 6.0 CMOS ±5.2 18 50 pF -40 to +125 74LV138 3-to-8 line decoder/demultiplexer; inverting 1.0 to 5.5 TTL ±12 12 50 pF -40 to +125 74LVC138 3-to-8 line decoder/demultiplexer; inverting 1.2 to 3.6 CMOS/ LVTTL ±24 2.7 50 pF -40 to +125 74LV139 Dual 2-to-4 line decoder/demultiplexer 1.0 to 5.5 TTL ±12 11 50 pF -40 to +125 74LVC139 Dual 2-to-4 line decoder/demultiplexer 1.2 to 3.6 74LVC1G18 1-to-2 demultiplexer (3-state) 1.65 to 5.5 CMOS/ LVTTL CMOS/ LVTTL ±24 2.5 50 pF -40 to +125 ±32 2.3 50 pF -40 to +125 HEF4028 1-of-10 decoder 4.5 to 15 CMOS ±2.4 30 50 pF -40 to +85 HEF4511 BCD to 7-segment latch/decoder/driver with lamp test input 4.5 to 15 CMOS -25/2.4 40 50 pF -40 to +85 HEF4514 4-to-16 decoder/demultiplexer with address latches 4.5 to 15 CMOS ±2.4 65 50 pF -40 to +85 HEF4543 BCD to 7-segment latch/decoder/driver with phase input 4.5 to 15 CMOS ±2.4 55 50 pF -40 to +85 HEF4555 Dual 1-to-4 line decoder/demultiplexer 4.5 to 15 CMOS ±2.4 30 50 pF -40 to +85 Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. NXP Logic selection guide 2016 79
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Logic selection guide 2016 Standard
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Standard Logic and Mini Logic: tune
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Transceivers 120 Standard logic pac
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NXP is the #1 volume leader For the
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What is configurable logic? Configu
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Our approach to quality At NXP, we
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Low-voltage families INCREASING PER
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Special features NXP offers a varie
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SOURCE TERMINATION What it does Imp
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OVERVOLTAGE-TOLERANT OUTPUTS 3-stat
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LIVE INSERTION What it does Enables
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OPEN-DRAIN OUTPUTS Open-drain outpu
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High-voltage families This section
Page 27 and 28: HEF4000B selection table (cont.) SO
Page 29 and 30: HC(T) selection table (cont.) TSSOP
Page 39 and 40: AHC(T) selection table (cont.) TSSO
Page 41 and 42: AHC(T) selection table (cont.) TSSO
Page 43 and 44: XC7 LOGIC XC7 devices are very high
Page 45 and 46: CBT(D) LOGIC CBT and CBTD bus switc
Page 47 and 48: LV selection table TSSOP SSOP SO DQ
Page 49 and 50: LVC selection table (cont.) TSSOP V
Page 55 and 56: ALVC selection table (cont.) TSSOP
Page 57 and 58: LVT selection table (cont.) TSSOP S
Page 59 and 60: AVC(M) LOGIC AVC and AVCM devices a
Page 61 and 62: AUP selection table (cont.) VSSOP M
Page 63 and 64: AXP LOGIC As the first logic family
Page 65 and 66: Product listing by function Analog
Page 67 and 68: Analog switches (cont.) Type number
Page 69 and 70: Buffers-inverters-drivers (cont.) T
Page 75 and 76: BUS SWITCHES Features and benefits
Page 77: Counters/frequency dividers (cont.)
Page 81 and 82: Digital multiplexers (cont.) Type n
Page 83 and 84: Flip-flops (cont.) Type number Desc
Page 85 and 86: Flip-flops (cont.) Type number Desc
Page 87 and 88: GATES This section includes AND gat
Page 89 and 90: Gates - Configurable Type number De
Page 91 and 92: Gates - NAND (cont.) Type number De
Page 93 and 94: Gates - OR (cont.) Type number Desc
Page 95 and 96: Latches-registered drivers (cont.)
Page 97 and 98: Level shifters-translators (cont.)
Page 99 and 100: PARITY GENERATORS/CHECKERS Features
Page 101 and 102: Schmitt triggers (cont.) Type numbe
Page 103 and 104: Shift registers - LED drivers (cont
Page 105 and 106: Transceivers (cont.) Type number De
Page 107 and 108: Q100 Standard Logic functions & pac
Page 109 and 110: Buffers/inverters (cont.) Features
Page 111 and 112: Counters/frequency dividers (cont.)
Page 113 and 114: Flip-flops (cont.) Features Package
Page 115 and 116: Gates (cont.) Features Package (suf
Page 117 and 118: Level shifters/translators Features
Page 119 and 120: Shift registers (cont.) Features Pa
Page 121 and 122: Standard logic packages Package suf
Page 123 and 124: Buffers/inverters (cont.) Features
Page 125 and 126: Digital decoders/demultiplexers Fea
Page 127 and 128: Gates (cont.) Features Package (suf
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Level shifters/translators Features
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The leadless advantage Today’s ul
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Nomenclature NXP's naming conventio
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SOT457 GV SOT505-2 DP Pinout Pinout
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SOT765-1 DC SOT833-1 GT Pinout Pino
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SOT902-2 GM SOT996 GD Pinout Pinout
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SOT1089 GF SOT1202 GS Pinout Pinout
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SOT815-1 BQ SOT402-1 PW Pinout Pino
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SOT337-1 DB SOT338-1 DB Pinout Pino
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SOT724-1 DS SOT1174 GM Pinout Pinou
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SOT556-1 DK SOT340-1 DB Pinout Pino
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Design tools NXP is committed to ma
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Evaluation board for configurable l
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Toshiba one gate IDT logic TC7 S Z
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