Logic selection guide 2016
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LVC <strong>selection</strong> table (cont.) TSSOP VSSOP SSOP SO DQFN BGA MicroPak PicoGate<br />
Type number Function Description<br />
74LVC595A<br />
74LVC623A<br />
74LVC646A<br />
74LVC74A<br />
74LVC821A<br />
74LVC827A<br />
74LVC841A<br />
74LVC86A<br />
74LVCH162374A<br />
74LVCH16541A<br />
74LVCH322244A<br />
74LVCH322245A<br />
74LVCH32244A<br />
74LVCH32245A<br />
74LVCH32373A<br />
74LVCH32374A<br />
74LVCU04A<br />
74LVCV2G66<br />
Shift register<br />
Transceiver<br />
Transceiver<br />
D-type flip-flop<br />
D-type flip-flop<br />
Buffer/inverter/<br />
driver<br />
Latch/registered<br />
driver<br />
EXCLUSIVE-OR<br />
gate<br />
D-type flip-flop<br />
Buffer/inverter/<br />
driver<br />
Buffer/inverter/<br />
driver<br />
Transceiver<br />
Buffer/inverter/<br />
driver<br />
Transceiver<br />
Latch/registered<br />
driver<br />
D-type flip-flop<br />
Buffer/inverter/<br />
driver<br />
Analog switch<br />
8-bit serial-in/parallel-out shift<br />
register with output storage<br />
register (3-state)<br />
Octal transceiver with dual<br />
enable (3-state)<br />
Octal registered transceiver<br />
(3-state)<br />
Dual D-type flip-flop with<br />
set and reset; positive-edge<br />
trigger<br />
10-bit D-type flip-flop;<br />
positive-edge trigger (3-state)<br />
10-bit buffer/line driver<br />
(3-state)<br />
10-bit D-type transparent<br />
latch (3-state)<br />
Quad 2-input EXCLUSIVE-OR<br />
gate<br />
16-bit D-type flip-flop<br />
with bus hold and 30 Ω<br />
termination resistors; positiveedge<br />
trigger (3-state)<br />
16-bit buffer/line driver with<br />
bus hold (3-state)<br />
32-bit buffer/line driver<br />
with bus hold and 30 Ω<br />
termination resistors (3-state)<br />
32-bit transceiver with bus<br />
hold and 30 Ω termination<br />
resistors (3-state)<br />
32-bit buffer/line driver with<br />
bus hold (3-state)<br />
32-bit transceiver with bus<br />
hold (3-state)<br />
32-bit D-type transparent<br />
latch (3-state)<br />
32-bit D-type flip-flop with<br />
bus hold; positive-edge<br />
trigger (3-state)<br />
Suffix<br />
DGG,<br />
PW<br />
Suffix<br />
DC<br />
Suffix<br />
DB,<br />
DL<br />
Suffix<br />
D<br />
Suffix<br />
BQ,<br />
BX<br />
• • •<br />
• • •<br />
• •<br />
• • • •<br />
• • • •<br />
• • • •<br />
• • • •<br />
• • • •<br />
• •<br />
• •<br />
Hex inverter; unbuffered • •<br />
Dual single-pole, single-throw<br />
analog switch; overvoltage<br />
tolerant<br />
Suffix<br />
EC, EV<br />
•<br />
•<br />
•<br />
•<br />
•<br />
•<br />
Suffix<br />
GD, GF,<br />
GM, GN,<br />
GS, GT,<br />
GX<br />
Suffix<br />
DP, GW,<br />
GV<br />
• •<br />
NXP <strong>Logic</strong> <strong>selection</strong> <strong>guide</strong> <strong>2016</strong><br />
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