Logic selection guide 2016

Recommendations

Info

Transceivers (cont.) Type number Description V CC (V) Logic switching levels Output drive capability t pd (ns) Number of bits f max (MHz) Output Load C L (Typ) 74LVTH2245 74LVT162245 74LVT16500 74LVT16501 Octal transceiver with bus hold and 30 Ω termination resistors (3-state) 16-bit transceiver with bus hold and 30 Ω termination resistors (3-state) 18-bit universal bus transceiver with bus hold; negative-edge trigger (3-state) 18-bit universal bus transceiver with bus hold; positive-edge trigger (3-state) 2.7 to 3.6 TTL ±12 3.2 8 150 50 pF 2.7 to 3.6 TTL ±12 2.5 16 150 50 pF 2.7 to 3.6 TTL -32 / +64 1.9 18 150 50 pF 2.7 to 3.6 TTL -32 / +64 1.9 18 150 50 pF 74LVT16543 16-bit registered transceiver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 2.2 16 150 50 pF 74LVT16646 16-bit registered transceiver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 1.9 16 150 50 pF 74LVT16652 16-bit registered transceiver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 1.9 16 150 50 pF 74LVT245 Octal transceiver (3-state) 2.7 to 3.6 TTL -32 / +64 2.4 8 150 50 pF 74LVT2952 Octal registered transceiver with 30 Ω termination resistors (3-state) 2.7 to 3.6 TTL -32 / +64 3.8 8 150 50 pF 74LVT543 Octal registered transceiver (3-state) 2.7 to 3.6 TTL -32 / +64 3 8 150 50 pF 74LVT543 Octal registered transceiver (3-state) 2.7 to 3.6 TTL -32 / +64 3 8 150 50 pF 74LVT640 Octal transceiver with bus hold; inverting (3-state) 2.7 to 3.6 TTL -32 / +64 2.4 8 150 50 pF 74LVT646 Octal registered transceiver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 3.8 8 150 50 pF 74LVT652 Octal registered transceiver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 3.7 8 150 50 pF 74LVTH322245 32-bit transceiver with bus hold and 30 Ω termination resistors (3-state) 2.7 to 3.6 TTL ±12 2.5 32 150 50 pF 74LVTH32245 32-bit transceiver with bus hold (3-state) 2.7 to 3.6 TTL -32 / +64 1.9 32 150 50 pF 74LVTN16245 16-bit transceiver (3-state) 2.7 to 3.6 TTL -32 / +64 1.9 16 150 50 pF 74VHC245 Octal transceiver (3-state) 2.0 to 5.5 CMOS ±8 3.5 8 60 50 pF 74VHCT245 Octal transceiver; TTL-enabled (3-state) 4.5 to 5.5 TTL ±8 5 8 60 50 pF Note: Selected package types only. Complete package listings are in the previous section and online at www.nxp.com/logic. 106 NXP Logic selection guide 2016
Q100 Standard Logic functions & packages Standard logic functions include options suitable for use at supply voltage between 1.0 V and 15 V. They provide a wide range of functions such as analog switches, buffers/inverters, bus switches, counters, decoders/de-multiplexers, multiplexers, flip-flops, gates, latches, level shifters, multivibrators, Schmitt triggers, shift registers and transceivers. Q100 Standard logic is available in leaded SO and TSSOP packages as well as the innovative leadless DQFN package. NXP’s DQFN packages include side-wettable flanks, making them suitable for automated optical inspection. The package suffixes used in the tables are for all logic families with the exception of HEF4000B. The suffixes for HEF4000B can be found under Standard Logic Packages. Analog switches Features Package (suffix) Type number Description Configuration V CC (V) R ON (W) R ON (FLAT) (W) T amb (°C) SOT108-1 (D) SOT402-1 (PW) SOT762-1 (BQ) SOT109-1 (D) SOT403-1 (PW) SOT763-1 (BQ) SOT137-1 (D) 74HC4051-Q100 Single-pole, octal-throw analog switch SP8T-Z 2.0 - 10.0 200 20 -40~125 • • • 74HCT4051-Q100 Single-pole, octal-throw analog switch; TTL-enabled SP8T-Z 4.5 - 5.5 225 20 -40~125 • • • 74HC4052-Q100 Dual single-pole, quad-throw analog switch SP4T-Z 2.0 - 10.0 200 20 -40~125 • • • 74HCT4052-Q100 74HC4053-Q100 74HCT4053-Q100 Dual single-pole, quad-throw analog switch; TTL-enabled Triple single-pole, double-throw analog switch Triple single-pole, double-throw analog switch; TTL-enabled SP4T-Z 4.5 - 5.5 200 20 -40~125 • • • SP8T-Z 2.0 - 10.0 200 20 -40~125 • • • SP8T-Z 4.5 - 5.5 200 20 -40~125 • • • 74HC4066-Q100 Quad single-pole, single-throw analog switch SPST-NO 2.0 - 10.0 105 23 -40~125 • • • 74HCT4066-Q100 Quad single-pole, single-throw analog switch; TTL-enabled SPST-NO 4.5 - 5.5 118 23 -40~125 • • • 74HC4851-Q100 Single-pole, octal-throw analog switch SP8T-Z 2.0 - 10.0 220 - -40~125 • • • 74HCT4851-Q100 Single-pole, octal-throw analog switch; TTL-enabled SP8T-Z 4.5 - 5.5 240 - -40~125 • • • 74HC4852-Q100 Dual single-pole, quad-throw analog switch SP4T-Z 2.0 - 10.0 220 - -40~125 • • • 74HCT4852-Q100 Dual single-pole, quad-throw analog switch; TTL-enabled SP4T-Z 4.5 - 5.5 240 - -40~125 • • • 74LV4052-Q100 Dual single-pole, quad-throw analog switch SP4T-Z 1.0 - 6.0 125 15 -40~125 • • 74LV4053-Q100 Triple single-pole, double-throw analog switch SPDT-Z 1.0 - 6.0 150 30 -40~125 • • • 74LVC4066-Q100 Quad single-pole, single-throw analog switch SPST-NO 1.65 - 5.5 15 1.5 -40~125 • • • HEF4051B-Q100 Single-pole, octal-throw analog switch SP8T-Z 4.5 - 15.5 175 30 -40~85 • • HEF4052B-Q100 Dual single-pole, quad-throw analog switch SP4T-Z 4.5 - 15.5 175 30 -40~85 • • HEF4053B-Q100 Triple single-pole, double-throw analog switch SPDT-Z 4.5 - 15.5 175 30 -40~85 • • HEF4066B-Q100 Quad single-pole, single-throw analog switch SPST-NO 4.5 - 15.5 175 20 -40~85 • HEF4067B-Q100 Single-pole, 16-throw analog switch SP16T-Z 4.5 - 15.5 175 20 -40~85 • NXP Logic selection guide 2016 107
Page 1 and 2:
Logic selection guide 2016 Standard
Page 3 and 4:
Standard Logic and Mini Logic: tune
Page 5 and 6:
Transceivers 120 Standard logic pac
Page 7 and 8:
NXP is the #1 volume leader For the
Page 9 and 10:
What is configurable logic? Configu
Page 11 and 12:
Our approach to quality At NXP, we
Page 13 and 14:
Low-voltage families INCREASING PER
Page 15 and 16:
Special features NXP offers a varie
Page 17 and 18:
SOURCE TERMINATION What it does Imp
Page 19 and 20:
OVERVOLTAGE-TOLERANT OUTPUTS 3-stat
Page 21 and 22:
LIVE INSERTION What it does Enables
Page 23 and 24:
OPEN-DRAIN OUTPUTS Open-drain outpu
Page 25 and 26:
High-voltage families This section
Page 27 and 28:
HEF4000B selection table (cont.) SO
Page 29 and 30:
HC(T) selection table (cont.) TSSOP
Page 31 and 32:
Page 33 and 34:
Page 35 and 36:
Page 37 and 38:
Page 39 and 40:
AHC(T) selection table (cont.) TSSO
Page 41 and 42:
AHC(T) selection table (cont.) TSSO
Page 43 and 44:
XC7 LOGIC XC7 devices are very high
Page 45 and 46:
CBT(D) LOGIC CBT and CBTD bus switc
Page 47 and 48:
LV selection table TSSOP SSOP SO DQ
Page 49 and 50:
LVC selection table (cont.) TSSOP V
Page 51 and 52:
Page 53 and 54:
Page 55 and 56: ALVC selection table (cont.) TSSOP
Page 57 and 58: LVT selection table (cont.) TSSOP S
Page 59 and 60: AVC(M) LOGIC AVC and AVCM devices a
Page 61 and 62: AUP selection table (cont.) VSSOP M
Page 63 and 64: AXP LOGIC As the first logic family
Page 65 and 66: Product listing by function Analog
Page 67 and 68: Analog switches (cont.) Type number
Page 69 and 70: Buffers-inverters-drivers (cont.) T
Page 75 and 76: BUS SWITCHES Features and benefits
Page 77 and 78: Counters/frequency dividers (cont.)
Page 79 and 80: Decoders demultiplexers (cont.) Typ
Page 81 and 82: Digital multiplexers (cont.) Type n
Page 83 and 84: Flip-flops (cont.) Type number Desc
Page 85 and 86: Flip-flops (cont.) Type number Desc
Page 87 and 88: GATES This section includes AND gat
Page 89 and 90: Gates - Configurable Type number De
Page 91 and 92: Gates - NAND (cont.) Type number De
Page 93 and 94: Gates - OR (cont.) Type number Desc
Page 95 and 96: Latches-registered drivers (cont.)
Page 97 and 98: Level shifters-translators (cont.)
Page 99 and 100: PARITY GENERATORS/CHECKERS Features
Page 101 and 102: Schmitt triggers (cont.) Type numbe
Page 103 and 104: Shift registers - LED drivers (cont
Page 105: Transceivers (cont.) Type number De
Page 109 and 110: Buffers/inverters (cont.) Features
Page 111 and 112: Counters/frequency dividers (cont.)
Page 113 and 114: Flip-flops (cont.) Features Package
Page 115 and 116: Gates (cont.) Features Package (suf
Page 117 and 118: Level shifters/translators Features
Page 119 and 120: Shift registers (cont.) Features Pa
Page 121 and 122: Standard logic packages Package suf
Page 123 and 124: Buffers/inverters (cont.) Features
Page 125 and 126: Digital decoders/demultiplexers Fea
Page 127 and 128: Gates (cont.) Features Package (suf
Page 129 and 130: Level shifters/translators Features
Page 131 and 132: The leadless advantage Today’s ul
Page 133 and 134: Nomenclature NXP's naming conventio
Page 135 and 136: SOT457 GV SOT505-2 DP Pinout Pinout
Page 137 and 138: SOT765-1 DC SOT833-1 GT Pinout Pino
Page 139 and 140: SOT902-2 GM SOT996 GD Pinout Pinout
Page 141 and 142: SOT1089 GF SOT1202 GS Pinout Pinout
Page 143 and 144: SOT815-1 BQ SOT402-1 PW Pinout Pino
Page 145 and 146: SOT337-1 DB SOT338-1 DB Pinout Pino
Page 147 and 148: SOT724-1 DS SOT1174 GM Pinout Pinou
Page 149 and 150: SOT556-1 DK SOT340-1 DB Pinout Pino
Page 151 and 152: Design tools NXP is committed to ma
Page 153 and 154: Evaluation board for configurable l
Page 155 and 156: Toshiba one gate IDT logic TC7 S Z
show all

Logic selection guide 2016

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?