PXA3xx Boot ROM Reference Manual - Marvell

PXA3xx Processor and Tavor ProcessorBoot ROM Reference ManualWhile the Boot ROM is running and is mapped to 0x0000_0000 - 0x0000_BFFF, external flashmemory mapped to this region is not accessible. Before handing control to any image, the BootROM remaps the 0x0000_0000 - 0x0000_BFFF address space to external flash memory on chipselect 0 to make access to this flash memory possible. Once this address space is remapped to theexternal flash, higher layers of software must accommodate the vector table by setting up a vectortable in an appropriate location depending on the usage model chosen. Refer to the specificprocessor developers manual for more details on the requirements for setting up the vector table.1.4 Boot ROM OverviewAfter reset, the Boot ROM performs the essential initialization including programming the clocks,GPIO settings, and the interrupt controller. The Boot ROM verifies whether the reset reason was areturn-from-hardware reset (HWR), Watchdog reset (WDR), or a resume-from-S3 power-state reset.NoteNoteAfter V3.20 Boot ROM, the Boot ROM does not perform verification to identify the lastreset transition. All Version 2.xx Boot ROMs perform this task. Therefore, for theapplication processors, only the PXA320 and PXA30x A1 perform this procedure asindicated in Figure 1.If the reset is not attributable to any of these reasons listed above, the Boot ROM uses the platformconfiguration data that is provided by the bootsource fuses to determine how to resume the platformfrom an S2/D3/C4 state or GPIO reset.For more details, refer to Chapter 2 and Chapter 3 of this document.Figure 1 shows the execution flow of the Boot ROM from reset. All processor resets are directed tothe Boot ROM, from where the appropriate path to resume or boot is determined.12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758Doc. No. MV-S301208-00 Rev. - PUBLIC RELEASE Copyright © 2010 MarvellPage 12