PXA3xx Boot ROM Reference Manual - Marvell

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PXA3xx Processor and Tavor ProcessorBoot ROM Reference Manual5.9.1 PXA32x Processor Register SettingsTable 17: PXA32x Processor Implementation SettingsBall Name Address ValueGPIO2 0x40E1_012C 0x0000_0001GPIO3 0x40E1_0130 0x0000_0001GPIO4 0x40E1_0134 0x0000_0001nXCVREN 0x40E1_0138 0x0000_1900nBE0 0x40E1_0214 0x0000_1800nBE1 0x40E1_0218 0x0000_1800nLUA 0x40E1_0234 0x0000_1900nLLA 0x40E1_0238 0x0000_1900DF_ADDR0 0x40E1_023C 0x0000_1800DF_ADDR1 0x40E1_0240 0x0000_1800DF_ADDR2 0x40E1_0244 0x0000_1800DF_ADDR3 0x40E1_0248 0x0000_1800DF_CLE_NOE 0x40E1_0204 0x0000_1800DF_ALE_nWE1 0x40E1_0208 0x0000_1801DF_IO0 0x40E1_024C 0x0000_1401DF_IO1 0x40E1_0254 0x0000_1401DF_IO2 0x40E1_025C 0x0000_1401DF_IO3 0x40E1_0264 0x0000_1401DF_IO4 0x40E1_026C 0x0000_1401DF_IO5 0x40E1_0274 0x0000_1401DF_IO6 0x40E1_027C 0x0000_1401DF_IO7 0x40E1_0284 0x0000_1401DF_IO8 0x40E1_0250 0x0000_1401DF_IO9 0x40E1_0258 0x0000_1401DF_IO10 0x40E1_0260 0x0000_1401DF_IO11 0x40E1_0268 0x0000_1401DF_IO12 0x40E1_0270 0x0000_1401DF_IO13 0x40E1_0278 0x0000_1401DF_IO14 0x40E1_0280 0x0000_1401DF_IO15 0x40E1_0288 0x0000_140112345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758Doc. No. MV-S301208-00 Rev. - PUBLIC RELEASE Copyright © 2010 MarvellPage 52
Table 18:Chip Select 2 SetupRegister Address Value FunctionSMEMC CSADRCFG2 0x4A00_0088 0x0032_0919 ––SMEMC MSC1 0x4A00_000C Bits [15:0] = 0x7FF8All others = DefaultThe ball values in Table 19 are in addition to the ball values in Table 17 and are only configured if theprocessor is configured for NAND boot support.Table 19: Additional PXA32x Processor Ball Values Set for NAND Platforms OnlyBall Name Address ValueDF_ALE_nWE2 0x40E1_021C [31:3] = Default; [2:0] = 1DF_nCS0 0x40E1_0224 [31:3] = Default; [2:0] = 1DF_nCS1 0x40E1_0228 [31:3] = Default; [2:0] = 1DF_nWE 0x40E1_022C [31:3] = Default; [2:0] = 1DF_nRE 0x40E1_0230 [31:3] = Default; [2:0] = 1Values in Table 20 are used for configuring the UART port for image download over UART.Table 20: FFUART PinsBall Name Address Value FunctionGPIO41 0x40E1_0438 0x0000_1042 FFRXDGPIO42 0x40E1_043C 0x0000_1042 FFTXDGPIO43 0x40E1_0440 0x0000_1042 FFCTSGPIO44 0x40E1_0444 0x0000_1042 FFDCDGPIO45 0x40E1_0448 0x0000_1042 FFDSRGPIO46 0x40E1_044C 0x0000_1042 FFRIGPIO47 0x40E1_0450 0x0000_1042 FFDTRGPIO48 0x40E1_0454 0x0000_1042 FFRTSValues in Table 21 are used for configuring the USB Client single-ended port for image downloadover USB.Table 21: USB Single Ended PinsBall Name Address Value FunctionGPIO97 0x40E1_054C 0x0000_1402 nOE2GPIO98 0x40E1_0550 0x0000_1402 VPO2GPIO99 0x40E1_0600 0x0000_1402 RCV2GPIO100 0x40E1_0604 0x0000_1402 VMO2GPIO102 0x40E1_060C 0x0000_1402 VM2GPIO103 0x40E1_0610 0x0000_1402 VP2GPIO104 0x40E1_0614 0x0000_1402 SPEED––12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758Copyright © 2010 Marvell PUBLIC RELEASE Doc. No. MV-S301208-00 Rev. -Page 53
Page 1 and 2: CoverMarvell® PXA3xx Processors an
Page 3 and 4: Table of Contents1 Boot ROM Functio
Page 5 and 6: 6.3.5 USB Vendor Request Package ..
Page 7 and 8: Figure 1:PXA3xx Top Level Boot ROM
Page 9 and 10: Table 42: Host Commands ...........
Page 11 and 12: 1 Boot ROM Functional Overview1.1 G
Page 13 and 14: Figure 1:PXA3xx Top Level Boot ROM
Page 15 and 16: Boot ROM Differences2 Boot ROM Diff
Page 17 and 18: Boot ROM DifferencesTIM/NTIM/OBM Su
Page 19 and 20: Boot ROM DifferencesPXA31x and Tavo
Page 21 and 22: Boot ROM DifferencesPXA31x and Tavo
Page 23 and 24: 3 Software RequirementsThis chapter
Page 25 and 26: Typedef struct S_Reloc{USHORT Heade
Page 27 and 28: 4 Methods for Platform Provisioning
Page 29 and 30: 4. If the same OEM boot module is u
Page 31 and 32: multiple versions of the Device Key
Page 34 and 35: PXA3xx Processor and Tavor Processo
Page 72 and 73: PXA3xx Processors and Tavor Process
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PXA3xx Processors and Tavor Process
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Marvell Semiconductor, Inc.700 Firs
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PXA3xx Boot ROM Reference Manual - Marvell

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