PXA3xx Boot ROM Reference Manual - Marvell

NoteNoteThe Marvell bad-block scheme is code used for NAND bad-block management. Thiscode is available as example code in the OBM source files. Contact your local FAE forBSP availability.5.2 Boot ROM NAND Device SupportThe Boot ROM for the PXA3xx Processor Family and Tavor Processor supports many different SLCNAND devices such as:• Large Block NAND x8 and x16• Small Block NAND x165.2.1 Boot ROM NAND Device RecognitionAn algorithm has been implemented to enable booting from different types of NAND devices. Thealgorithm works as follows:1. Boot ROM issues the reset command 0xFFNoteNoteThis reset command is required as part of the ONFI specification. NAND devices thatrequire the reset command are only supported natively by V3.32 Boot ROM and later.See Table 1, Version 2.xx and Version 3.xx High Level Differences, on page 15 foroverview of processors that support this feature.2. The Boot ROM issues a read_id command to the device retrieving two bytes of data.3. The two bytes (manufacturer ID and device ID) are compared against the small block codes inTable 11. All Boot ROM versions support these devices.• If the device is a small block device then the Boot ROM configures the NAND controller forsmall block operation with a 512-Byte page size and 16 KB block size.12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758Copyright © 2010 Marvell PUBLIC RELEASE Doc. No. MV-S301208-00 Rev. -Page 39