PXA3xx Boot ROM Reference Manual - Marvell

Table 18:Chip Select 2 SetupRegister Address Value FunctionSMEMC CSADRCFG2 0x4A00_0088 0x0032_0919 ––SMEMC MSC1 0x4A00_000C Bits [15:0] = 0x7FF8All others = DefaultThe ball values in Table 19 are in addition to the ball values in Table 17 and are only configured if theprocessor is configured for NAND boot support.Table 19: Additional PXA32x Processor Ball Values Set for NAND Platforms OnlyBall Name Address ValueDF_ALE_nWE2 0x40E1_021C [31:3] = Default; [2:0] = 1DF_nCS0 0x40E1_0224 [31:3] = Default; [2:0] = 1DF_nCS1 0x40E1_0228 [31:3] = Default; [2:0] = 1DF_nWE 0x40E1_022C [31:3] = Default; [2:0] = 1DF_nRE 0x40E1_0230 [31:3] = Default; [2:0] = 1Values in Table 20 are used for configuring the UART port for image download over UART.Table 20: FFUART PinsBall Name Address Value FunctionGPIO41 0x40E1_0438 0x0000_1042 FFRXDGPIO42 0x40E1_043C 0x0000_1042 FFTXDGPIO43 0x40E1_0440 0x0000_1042 FFCTSGPIO44 0x40E1_0444 0x0000_1042 FFDCDGPIO45 0x40E1_0448 0x0000_1042 FFDSRGPIO46 0x40E1_044C 0x0000_1042 FFRIGPIO47 0x40E1_0450 0x0000_1042 FFDTRGPIO48 0x40E1_0454 0x0000_1042 FFRTSValues in Table 21 are used for configuring the USB Client single-ended port for image downloadover USB.Table 21: USB Single Ended PinsBall Name Address Value FunctionGPIO97 0x40E1_054C 0x0000_1402 nOE2GPIO98 0x40E1_0550 0x0000_1402 VPO2GPIO99 0x40E1_0600 0x0000_1402 RCV2GPIO100 0x40E1_0604 0x0000_1402 VMO2GPIO102 0x40E1_060C 0x0000_1402 VM2GPIO103 0x40E1_0610 0x0000_1402 VP2GPIO104 0x40E1_0614 0x0000_1402 SPEED––12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758Copyright © 2010 Marvell PUBLIC RELEASE Doc. No. MV-S301208-00 Rev. -Page 53