PXA3xx Boot ROM Reference Manual - Marvell

More documents

Recommendations

Info

PXA3xx Processor and Tavor ProcessorBoot ROM Reference ManualTable 2:Version 2.xx ISRAM Usage (Continued)ISRAM Address Size Usage0x5C00_8000 48 KB Boot ROM data/stack0x5C01_4000 Rest of ISRAM Image downloadTable 3:Version 3.xx ISRAM UsageISRAM Address Size Usage0x5C00_0000 32 KB Caddo0x5C00_8000 44 KB Boot ROM data/stack0x5C01_3000 Rest of ISRAM Image download2.3.2 OBM UsageVersion 2.xx has fixed offsets for OBM images based on flash type used. The area in the Static ChipSelect 0 (nCS0) from 0x0 to 0xBFFF is dual-mapped to either Boot ROM or external flash, which canmake programming difficult. The Boot ROM also uses the first two words for its own operations sothe OEM system boot module (OSBM) images had to be manually shifted when programming.Table 4:Version 2.xx OBM UsageBoot Device OBM location in device Runtime location of OBMChip Select 2 - nCS2 Block 0 offset 0x0 0x1000_0000NAND device on ND_nCS0 Block 0 offset 0x8 0x5C01_4000Version 3.xx is backward compatible with version 2.xx. Certain requirements, such as the boot statefuses, must be programmed and the offsets in Table 5 must be adhered to. For NAND Flash, theOBM size is limited to one block.Table 5:Version 3.xx OBM UsageBoot Device OBM location in device Runtime location of OBMChip Select 0 - nCS0 block 0 offset 0xC000 0x0000_C000Chip Select 2 - nCS2 block 0 offset 0x0 0x1000_0000NAND device on ND_nCS0 block 0 offset 0x0 0x5C01_30002.4 PXA31x and Tavor Processor Auto-BootAll PXA3xx processors and Tavor processors have been pre-programmed prior to customershipments, which requires customers to specify the required boot memory such as XIP NOR Flashboot from nCS2 and x8 or x16 NAND boot devices.However, the PXA31x A1 and Tavor B0 stepping do not operate in this way. These processors areshipped without the boot type fuses configured, which allows flexibility in customer builds for usingthe same device in multiple platforms with different boot-memory configurations.Doc. No. MV-S301208-00 Rev. - PUBLIC RELEASE Copyright © 2010 MarvellPage 18
Boot ROM DifferencesPXA31x and Tavor Processor Auto-BootAuto-boot is a process whereby the Boot ROM probes all the valid boot devices for a valid headerfile (either a TIM or NTIM). Once this header is found, it is used to boot the system. The Boot ROMdoes not search for multiple headers. The first valid header that is found is used to boot the system.The boot memories are probed in the following order:• XIP on nCS2• XIP on nCS0 (XIP NOR only; not Managed NAND + mDOC)• x16 NAND on ND_nCS0• x8 NAND on ND_nCS0• Samsung OneNAND on nCS2• Sandisk mDOC on nCS2If a valid TIM or NTIM is not found, then the Boot ROM waits for a download operation over USB orUART. This operation would be downloading an image from a host over a USB or UART to theplatform. If the TIM or NTIM is not found, this would indicate that the flash memory is notprogrammed.NoteIf the Boot ROM does not find a valid header and the image download is successful, thesubsequent boot probes each boot memory (as described above) but now the BootROM finds the valid TIM/NTIM and the boot process continues.2.4.1 Auto-Boot on Non-Trusted PlatformsThe auto-boot process described in Section 2.4, PXA31x and Tavor Processor Auto-Boot occurs forevery boot or reset exit on non-trusted platforms. Below is the list of resets and mode exits:• SOD - start of day• Hardware reset• Watchdog reset• GPIO reset• S2/D3 exit**• S3/D4 exit**Software may optionally configure a D3 resume to internal SRAM. If enabled, then the“probing” is bypassed. This option is enabled in the NTIM/TIM package.NoteFor PXA32x C0 processor, Auto-Boot feature does not allow for backward compatibitybetween Boot ROM version 2.xx and version 3.xx. In Auto-Boot mode, the PXA32x C0processor requires the same memory addresses as the PXA31x processor. ThePXA32x C0 is fully backward compatible with PXA32x B2 in fused mode only.2.4.2 Auto-Boot on Trusted PlatformsThe auto-boot process described in Section 2.4, PXA31x and Tavor Processor Auto-Boot occursonly for the first boot if a valid TIM is found for a Trusted Boot. If the Boot ROM fails to find a validheader, then the Boot ROM waits for an image download to occur.Once a TIM is found and has been successfully validated, the platform is bound, which means thatthe fuses have been configured permanently. All subsequent boots are fused boots and the probing(auto-boot feature) of each memory device does not occur.Copyright © 2010 Marvell PUBLIC RELEASE Doc. No. MV-S301208-00 Rev -Page 19
Page 1 and 2: CoverMarvell® PXA3xx Processors an
Page 3 and 4: Table of Contents1 Boot ROM Functio
Page 5 and 6: 6.3.5 USB Vendor Request Package ..
Page 7 and 8: Figure 1:PXA3xx Top Level Boot ROM
Page 9 and 10: Table 42: Host Commands ...........
Page 11 and 12: 1 Boot ROM Functional Overview1.1 G
Page 13 and 14: Figure 1:PXA3xx Top Level Boot ROM
Page 15 and 16: Boot ROM Differences2 Boot ROM Diff
Page 17: Boot ROM DifferencesTIM/NTIM/OBM Su
Page 21 and 22: Boot ROM DifferencesPXA31x and Tavo
Page 23 and 24: 3 Software RequirementsThis chapter
Page 25 and 26: Typedef struct S_Reloc{USHORT Heade
Page 27 and 28: 4 Methods for Platform Provisioning
Page 29 and 30: 4. If the same OEM boot module is u
Page 31 and 32: multiple versions of the Device Key
Page 34 and 35: PXA3xx Processor and Tavor Processo
Page 68 and 69:
PXA3xx Processor and Tavor Processo
Page 70 and 71:
PXA3xx Processor and Tavor Processo
Page 72 and 73:
PXA3xx Processors and Tavor Process
Page 74 and 75:
Page 76 and 77:
Page 78 and 79:
Page 80 and 81:
Page 82 and 83:
Page 84 and 85:
Page 86 and 87:
Page 88 and 89:
Page 90 and 91:
Page 92 and 93:
Page 94 and 95:
Page 96 and 97:
Page 98 and 99:
Page 100 and 101:
Page 102 and 103:
Page 104 and 105:
Page 106 and 107:
Page 108 and 109:
Page 110 and 111:
Page 112:
Marvell Semiconductor, Inc.700 Firs
show all

PXA3xx Boot ROM Reference Manual - Marvell

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?