PXA3xx Boot ROM Reference Manual - Marvell

PXA3xx Processor Family and Tavor ProcessorBoot ROM Reference Manual5 Boot ROM Implementation Details........................................................................... 355.1 Non-Trusted Boot Address Map................................................................................................ 355.1.1 Trusted Boot Address Map............................................................................................................. 365.1.2 NTIM/TIM Execution....................................................................................................................... 365.1.3 Requirements for the Wireless Trusted Module Save State........................................................... 375.1.4 Specific Requirements for NAND Platforms ................................................................................... 385.2 Boot ROM NAND Device Support............................................................................................. 395.2.1 Boot ROM NAND Device Recognition............................................................................................ 395.3 XIP Flash Support ..................................................................................................................... 415.3.1 NOR Flash One-Time Programmable Register Usage .................................................................. 425.4 Managed NAND Memory Support ............................................................................................ 425.5 OneNAND Support.................................................................................................................... 435.5.1 Exiting Low Power Mode and Resets with OneNAND ................................................................... 445.6 mDOC Support.......................................................................................................................... 455.6.1 Exiting Low Power Mode and Resets with mDOC ......................................................................... 455.7 Internal SRAM Usage ............................................................................................................... 465.8 Handling Power Mode and Reset Transitions........................................................................... 465.8.1 Platform Boot Process for Watchdog Reset, Power on Reset, Low Power Exit, and GPIO Reset 485.8.2 S2/D3/C4 Resume Requirements .................................................................................................. 485.9 Boot ROM: Processor-Specific Configurations ......................................................................... 505.9.1 PXA32x Processor Register Settings ............................................................................................. 525.9.2 Other Registers .............................................................................................................................. 545.10 PXA31x Processor Register Settings........................................................................................ 545.11 PXA30x Processor Register Settings........................................................................................ 565.12 Tavor Processor Implementation Details .................................................................................. 585.13 Error Conditions ........................................................................................................................ 605.14 Hints And Tips........................................................................................................................... 606 Non-Trusted Image Module ...................................................................................... 636.1 Non-Trusted Image Module Format .......................................................................................... 646.1.1 Version Information ........................................................................................................................ 646.1.2 Flash Information............................................................................................................................ 656.1.3 NTIM Sizing Information ................................................................................................................. 656.1.4 Image Information Array ................................................................................................................. 656.1.5 Reserved[SizeOfReserved] ............................................................................................................ 666.2 Reserved Area .......................................................................................................................... 666.2.1 Reserved Area Header................................................................................................................... 666.2.2 Reserved Area Packages............................................................................................................... 666.3 Predefined Packages for Reserved Area.................................................................................. 676.3.1 GPIO Packages.............................................................................................................................. 676.3.2 UART/USB Protocol Packages ...................................................................................................... 686.3.3 DDR Package................................................................................................................................. 686.3.4 Resume Package ........................................................................................................................... 68Doc. No. MV-S301208-00 Rev. - PUBLIC RELEASE Copyright © 2010 MarvellPage 4