PXA3xx Boot ROM Reference Manual - Marvell

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PXA3xx Processor and Tavor ProcessorBoot ROM Reference ManualNoteNoteIf the Boot ROM fails to find the sleep-resume structure, then the OBM code fromNAND Block 0 is copied back into iSRAM at address 0x5C01_3000.Using the sleep struct() to manage the resume process eliminates the Boot ROM from reloading theOBM code from NAND Block 0 thus providing a shorter exit latency. As noted above, if the struct() isnot found, then the resume period is extended by the time necessary to reload OBM.5.9 Boot ROM: Processor-Specific ConfigurationsThe following tables provide implementation settings for the PXA3xx Processor Family and Tavorprocessor.NoteNoteThe Boot ROM configures the USB and UART ports as defined in this section. Ifanother UART port is required, then the default port must be unconfigured. Thisunconfiguration can be managed using predefined packages in the NTIM/TIM header.Refer to Section 6.3, “Predefined Packages for Reserved Area”. Both ports (USB andFFUART) cannot be disabled.PXA32x Boot ROM Register configurations:• Table 17, “PXA32x Processor Implementation Settings"• Table 18, “Chip Select 2 Setup"• Table 19, “Additional PXA32x Processor Ball Values Set for NAND Platforms Only"• Table 20, “FFUART Pins"• Table 21, “USB Single Ended Pins"• Table 22, “During Sleep (S3/D3/C4 mode) Resume"PXA31x Boot ROM Register configurations:• Table 23, “PXA31x Processor Implementation Settings"• Table 24, “Additional PXA31x Processor Ball Values Set for NAND Platforms Only"• Table 25, “USB Port ULPI Pins"• Table 26, “FFUART Pins"PXA30x Boot ROM Register configurations:• Table 27, “PXA30x Processor Implementation Settings"• Table 28, “Chip Select 2 Setup"• Table 29, “Additional PXA30x Processor Ball Values Set for NAND Platforms Only"• Table 30, “FFUART Pins"Tavor Boot ROM Register configurations:• Table 32, “Tavor Processor Register Settings"• Table 33, “Additional Tavor Processor Ball Values Set for NAND Platforms Only"• Table 34, “FFUART Pins (Primary Location)"• Table 35, “FFUART Pins (Secondary Location)"• Table 36, “USB 2.0 Pins"12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758Doc. No. MV-S301208-00 Rev. - PUBLIC RELEASE Copyright © 2010 MarvellPage 50
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758Copyright © 2010 Marvell PUBLIC RELEASE Doc. No. MV-S301208-00 Rev. -Page 51
Page 1 and 2: CoverMarvell® PXA3xx Processors an
Page 3 and 4: Table of Contents1 Boot ROM Functio
Page 5 and 6: 6.3.5 USB Vendor Request Package ..
Page 7 and 8: Figure 1:PXA3xx Top Level Boot ROM
Page 9 and 10: Table 42: Host Commands ...........
Page 11 and 12: 1 Boot ROM Functional Overview1.1 G
Page 13 and 14: Figure 1:PXA3xx Top Level Boot ROM
Page 15 and 16: Boot ROM Differences2 Boot ROM Diff
Page 17 and 18: Boot ROM DifferencesTIM/NTIM/OBM Su
Page 19 and 20: Boot ROM DifferencesPXA31x and Tavo
Page 21 and 22: Boot ROM DifferencesPXA31x and Tavo
Page 23 and 24: 3 Software RequirementsThis chapter
Page 25 and 26: Typedef struct S_Reloc{USHORT Heade
Page 27 and 28: 4 Methods for Platform Provisioning
Page 29 and 30: 4. If the same OEM boot module is u
Page 31 and 32: multiple versions of the Device Key
Page 34 and 35: PXA3xx Processor and Tavor Processo
Page 72 and 73: PXA3xx Processors and Tavor Process
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PXA3xx Processors and Tavor Process
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Marvell Semiconductor, Inc.700 Firs
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PXA3xx Boot ROM Reference Manual - Marvell

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