PXA3xx Boot ROM Reference Manual - Marvell

PXA3xx Processor Family and Tavor ProcessorBoot ROM Reference ManualList of TablesTable 1: Version 2.xx and Version 3.xx High Level Differences .................................................................... 15Table 2: Version 2.xx ISRAM usage .............................................................................................................. 18Table 3: Version 3.xx ISRAM Usage ............................................................................................................. 18Table 4: Version 2.xx OBM Usage................................................................................................................. 19Table 5: Version 3.xx OBM usage ................................................................................................................. 19Table 6: Relocation Table Addresses ............................................................................................................ 24Table 7: Non-Trusted Image Module Locations............................................................................................. 35Table 8: OEM Boot Module (OBM) locations when No NTIM is used............................................................ 35Table 9: Trusted Image Module Locations for Trusted Boot.......................................................................... 36Table 10: OEM Boot Module Sizes Without Marvell Bad Block Management................................................. 38Table 11: Small Block Devices ........................................................................................................................ 40Table 12: NAND Flash Controller Initial Register Settings............................................................................... 41Table 13: NAND Command Set....................................................................................................................... 41Table 14: Flash Commands Supported by the Boot ROM...............................................................................42Table 15: OneNAND Device ID Support.......................................................................................................... 44Table 16: Overview of Resets and Power Modes............................................................................................ 46Table 17: PXA32x Processor Implementation Settings ................................................................................... 52Table 18: Chip Select 2 Setup ......................................................................................................................... 53Table 19: Additional PXA32x Processor Ball Values Set for NAND Platforms Only........................................ 53Table 20: FFUART Pins................................................................................................................................... 53Table 21: USB Single Ended Pins ................................................................................................................... 53Table 22: During Sleep (S3/D3/C4 mode) Resume......................................................................................... 54Table 23: PXA31x Processor Implementation Settings ................................................................................... 54Table 24: Additional PXA31x Processor Ball Values Set for NAND Platforms Only........................................ 55Table 25: USB Port ULPI Pins ......................................................................................................................... 55Table 26: FFUART Pins................................................................................................................................... 55Table 27: PXA30x Processor Implementation Settings ................................................................................... 56Table 28: Chip Select 2 Setup ......................................................................................................................... 57Table 29: Additional PXA30x Processor Ball Values Set for NAND Platforms Only........................................ 57Table 30: FFUART Pins................................................................................................................................... 57Table 31: USB Single Ended Pins ................................................................................................................... 57Table 32: Tavor Processor Register Settings .................................................................................................. 58Table 33: Additional Tavor Processor Ball Values Set for NAND Platforms Only............................................ 59Table 34: FFUART Pins (Primary Location)..................................................................................................... 59Table 35: FFUART Pins (Secondary Location)................................................................................................ 59Table 36: USB 2.0 Pins.................................................................................................................................... 59Table 37: BootFlashSign Definitions................................................................................................................ 65Table 38: Reserved Area Predefined Package ID’s ........................................................................................ 69Table 39: BootFlashSign Definitions................................................................................................................ 73Table 40: Reserved Area Predefined Package ID’s ........................................................................................ 78Table 41: Preamble.......................................................................................................................................... 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