PXA3xx Boot ROM Reference Manual - Marvell

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PXA3xx Processor and Tavor ProcessorBoot ROM Reference Manual5.11 PXA30x Processor Register SettingsTable 27 and Table 28 provide implementation settings for the PXA30x processor.Table 27: PXA30x Processor Implementation SettingsBall Name Address ValueGPIO0 0x40E1_00B4 0x0000_1401GPIO1 0x40E1_00B8 0x0000_1501GPIO2 0x40E1_00BC 0x0000_1501nBE0 0x40E1_0204 0x0000_1400nBE1 0x40E1_0208 0x0000_1400nLUA 0x40E1_0244 0x0000_1500nLLA 0x40E1_0254 0x0000_1500DF_ADDR0 0x40E1_0210 0x0000_1400DF_ADDR1 0x40E1_0214 0x0000_1400DF_ADDR2 0x40E1_0218 0x0000_1400DF_ADDR3 0x40E1_021C 0x0000_1400DF_CLE_NOE 0x40E1_0240 0x0000_1500DF_ALE_nWE 0x40E1_020C 0x0000_1501DF_IO0 0x40E1_0220 0x0000_1801DF_IO1 0x40E1_0228 0x0000_1801DF_IO2 0x40E1_0230 0x0000_1801DF_IO3 0x40E1_0238 0x0000_1801DF_IO4 0x40E1_0258 0x0000_1801DF_IO5 0x40E1_0260 0x0000_1801DF_IO6 0x40E1_0268 0x0000_1801DF_IO7 0x40E1_0270 0x0000_1801DF_IO8 0x40E1_0224 0x0000_1801DF_IO9 0x40E1_022C 0x0000_1801DF_IO10 0x40E1_0234 0x0000_1801DF_IO11 0x40E1_023C 0x0000_1801DF_IO12 0x40E1_025C 0x0000_1801DF_IO13 0x40E1_0264 0x0000_1801DF_IO14 0x40E1_026C 0x0000_1801DF_IO15 0x40E1_0274 0x0000_180112345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758Doc. No. MV-S301208-00 Rev. - PUBLIC RELEASE Copyright © 2010 MarvellPage 56
Table 28:Chip Select 2 SetupRegister Address Value FunctionSMEMC_CSADRCFG_2 0x4A00_0088 0x00320919 ––SMEMC_MSC1 0x4A00_000C Bits [15:0] = 0x7FF8All others = DefaultThese configurations are in addition to the ones described in Table 29 and are only configured if theprocessor is configured for NAND boot support.Table 29: Additional PXA30x Processor Ball Values Set for NAND Platforms OnlyBall Name Address ValueDF_nCS0 0x40E1_0248 [31:3] = Default; [2:0] = 1DF_nCS1 0x40E1_0278 [31:3] = Default; [2:0] = 1DF_nWE 0x40E1_00CC [31:3] = Default; [2:0] = 1DF_nRE 0x40E1_0200 [31:3] = Default; [2:0] = 1DF_nCS0 0x40E1_0248 [31:3] = Default; [2:0] = 1Ball_DF_INT_RnB 0x40E1_00C8 0x0000_1500Values in Table 30 are used for configuring the UART port for image download over UART.Table 30: FFUART PinsBall Name Address Value FunctionGPIO30 0x40E1_040C 0x0000_1402 FFRXDGPIO31 0x40E1_0410 0x0000_1402 FFTXDGPIO32 0x40E1_0414 0x0000_1502 FFCTSGPIO33 0x40E1_0418 0x0000_1502 FFDCDGPIO34 0x40E1_041C 0x0000_1502 FFDSRGPIO35 0x40E1_0420 0x0000_1502 FFRIGPIO36 0x40E1_0424 0x0000_1502 FFDTRGPIO37 0x40E1_0428 0x0000_1502 FFRTSValues in Table 31 are used for configuring the USB client single-ended port for image downloadover USB.Table 31: USB Single Ended PinsBall Name Address Value FunctionGPIO99 0x40E1_0600 0x0000_1402 nOE2GPIO100 0x40E1_0604 0x0000_1402 VPO2GPIO101 0x40E1_0608 0x0000_1402 RCV2GPIO102 0x40E1_060C 0x0000_1402 VMO2––12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758Copyright © 2010 Marvell PUBLIC RELEASE Doc. No. MV-S301208-00 Rev. -Page 57
Page 1 and 2:
CoverMarvell® PXA3xx Processors an
Page 3 and 4:
Table of Contents1 Boot ROM Functio
Page 5 and 6: 6.3.5 USB Vendor Request Package ..
Page 7 and 8: Figure 1:PXA3xx Top Level Boot ROM
Page 9 and 10: Table 42: Host Commands ...........
Page 11 and 12: 1 Boot ROM Functional Overview1.1 G
Page 13 and 14: Figure 1:PXA3xx Top Level Boot ROM
Page 15 and 16: Boot ROM Differences2 Boot ROM Diff
Page 17 and 18: Boot ROM DifferencesTIM/NTIM/OBM Su
Page 19 and 20: Boot ROM DifferencesPXA31x and Tavo
Page 21 and 22: Boot ROM DifferencesPXA31x and Tavo
Page 23 and 24: 3 Software RequirementsThis chapter
Page 25 and 26: Typedef struct S_Reloc{USHORT Heade
Page 27 and 28: 4 Methods for Platform Provisioning
Page 29 and 30: 4. If the same OEM boot module is u
Page 31 and 32: multiple versions of the Device Key
Page 34 and 35: PXA3xx Processor and Tavor Processo
Page 72 and 73: PXA3xx Processors and Tavor Process
Page 106 and 107:
PXA3xx Processors and Tavor Process
Page 108 and 109:
Page 110 and 111:
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Marvell Semiconductor, Inc.700 Firs
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PXA3xx Boot ROM Reference Manual - Marvell

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