PXA3xx Boot ROM Reference Manual - Marvell

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PXA3xx Processor and Tavor ProcessorBoot ROM Reference ManualWhile the Boot ROM is running and is mapped to 0x0000_0000 - 0x0000_BFFF, external flashmemory mapped to this region is not accessible. Before handing control to any image, the BootROM remaps the 0x0000_0000 - 0x0000_BFFF address space to external flash memory on chipselect 0 to make access to this flash memory possible. Once this address space is remapped to theexternal flash, higher layers of software must accommodate the vector table by setting up a vectortable in an appropriate location depending on the usage model chosen. Refer to the specificprocessor developers manual for more details on the requirements for setting up the vector table.1.4 Boot ROM OverviewAfter reset, the Boot ROM performs the essential initialization including programming the clocks,GPIO settings, and the interrupt controller. The Boot ROM verifies whether the reset reason was areturn-from-hardware reset (HWR), Watchdog reset (WDR), or a resume-from-S3 power-state reset.NoteNoteAfter V3.20 Boot ROM, the Boot ROM does not perform verification to identify the lastreset transition. All Version 2.xx Boot ROMs perform this task. Therefore, for theapplication processors, only the PXA320 and PXA30x A1 perform this procedure asindicated in Figure 1.If the reset is not attributable to any of these reasons listed above, the Boot ROM uses the platformconfiguration data that is provided by the bootsource fuses to determine how to resume the platformfrom an S2/D3/C4 state or GPIO reset.For more details, refer to Chapter 2 and Chapter 3 of this document.Figure 1 shows the execution flow of the Boot ROM from reset. All processor resets are directed tothe Boot ROM, from where the appropriate path to resume or boot is determined.12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758Doc. No. MV-S301208-00 Rev. - PUBLIC RELEASE Copyright © 2010 MarvellPage 12
Figure 1:PXA3xx Top Level Boot ROM Flow1.4.1 Boot Process for Programmed DeviceYesPerform platformspecific sleepresume processYesPower On / HWResetRead bootsource fuses to determine platformconfiguration and perform necessary setupIs this a S2resume?Is this an S3 resume, HW reset, orwatch dog reset?Is this a GPIOreset?Transfer control to OBMThe Boot ROM identifies the platform configuration fuses and transitions to the external flash. Forplatforms using NAND flash, the OEM boot module (OBM) is copied from Block 0 of the NAND flashto internal SRAM at and control is transferred to the OBM. For platforms using NOR flash, control istransferred to the external flash on nCS2 of the DFI bus. See Figure 2 (Boot Process Flow Chart).NoNoNoYesProgrammedDevice BootProcess12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758Copyright © 2010 Marvell PUBLIC RELEASE Doc. No. MV-S301208-00 Rev. -Page 13
Page 1 and 2: CoverMarvell® PXA3xx Processors an
Page 3 and 4: Table of Contents1 Boot ROM Functio
Page 5 and 6: 6.3.5 USB Vendor Request Package ..
Page 7 and 8: Figure 1:PXA3xx Top Level Boot ROM
Page 9 and 10: Table 42: Host Commands ...........
Page 11: 1 Boot ROM Functional Overview1.1 G
Page 15 and 16: Boot ROM Differences2 Boot ROM Diff
Page 17 and 18: Boot ROM DifferencesTIM/NTIM/OBM Su
Page 19 and 20: Boot ROM DifferencesPXA31x and Tavo
Page 21 and 22: Boot ROM DifferencesPXA31x and Tavo
Page 23 and 24: 3 Software RequirementsThis chapter
Page 25 and 26: Typedef struct S_Reloc{USHORT Heade
Page 27 and 28: 4 Methods for Platform Provisioning
Page 29 and 30: 4. If the same OEM boot module is u
Page 31 and 32: multiple versions of the Device Key
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PXA3xx Processors and Tavor Process
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Marvell Semiconductor, Inc.700 Firs
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PXA3xx Boot ROM Reference Manual - Marvell

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