PXA3xx Boot ROM Reference Manual - Marvell

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PXA3xx Processor and Tavor ProcessorBoot ROM Reference ManualTable 11:Small Block Devices4. For unknown small-block devices, the Boot ROM issues another read_id retrieving the 4th byteof data from the device.• The Boot ROM uses the information returned in the 4th byte to determine the page and blocksize of the NAND device. Bits 1 and 0 for the page size and bits 5 and 4 for the block size.Refer to Table 5, Version 3.xx OBM usage, on page 19.• The Boot ROM does NOT use the manufacturer and device codes for Large Block NANDconfiguration. The NFC is configured for large block based on the device parameters.• The NFC has a limit of 2048Byte page size.5. The Boot ROM then configures the command set for the appropriate NAND device (based onthe above steps) and continues with normal read operation.NoteManufacturerSamsungToshibaNoteHynixST MicroManufacturerCode0xEC0x980xAD0x20Device Codes0x71, 0x78, 0x79, 0x72, 0x74,0x36, 0x76, 0x46, 0x56, 0x35,0x75, 0x45, 0x55, 0x33, 0x73,0x43, 0x53, 0x39, 0xE6, 0x49,0x590x46, 0x79, 0x75, 0x73, 0x72,0xE60x76, 0x56, 0x36, 0x46, 0x75,0x55, 0x35, 0x45,0x73, 0x53, 0x490x73, 0x35, 0x75, 0x45,0x55, 0x76, 0x36, 0x46,0x56, 0x79, 0x39, 0x49,0x59This was originally documented as the Boot ROM expecting 0x15 for x8 large blockNAND and 0x55 for x16 large block NAND devices. Although the entire 4th byte is readfrom the NAND device, the Boot ROM uses only bits 0, 1, 4, and 5, not the entire byte(all 8 bits) to configure the appropriate memory device.12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758Doc. No. MV-S301208-00 Rev. - PUBLIC RELEASE Copyright © 2010 MarvellPage 40
Figure 8:Electronic Signature RequirementsElectronic Signature RequirementsBlock SizeBlock SizeDecodedPage SizePage SizeDecoderIO7 IO6 IO5 IO4 IO3 IO2 IO1 IO00 0 64K 0 0 Not Supported0 1 128K 0 1 2K1 0 Not Supported 1 0 Not Supported1 1 Not Supported 1 1 Not SupportedThe NAND Flash Controller (NFC) is set up for the appropriate NAND configuration as noted inTable 12, “NAND Flash Controller Initial Register Settings". NDCR[DWIDTH_C] andNDCR[DWIDTH_M] are configured by the Boot ROM depending on the boot configuration SKU ofthe processor.Table 12: NAND Flash Controller Initial Register SettingsRegisterValue for Small BlockOperationNoteNDCR[DWIDTH_C] andNDCR[DWIDTH_M] (bits27:26) initialsettings are determined by the bootstate fusesNote5.3 XIP Flash Support0xCC02_1FFFValue for Large BlockOperation0xCD04_1FFFTiming register 0 0x003F_3F3F 0x003F_3F3FTiming register 1 0x1FF0_C0FF 0x1FF0_C0FFTable 13:NAND Command SetCommand Small Block Command Code Large Block Command CodeRead 0x0000_ 0x3000Read Status 0x0070 0x0070Read ID 0x0090 0x0090Some NAND devices power up with the blocks in a locked state. To ensure the blockscan be unlocked with software, refer to the NFC chapter of the PXA3xx ProcessorFamily Vol. II: Memory Controller Configuration Developers Manual.The processor Boot ROM supports NOR Flash memory on the data flash interface (DFI) bus. Flashis supported via a command set, not through a particular JEDEC ID. See Table 14 for supportedcommands.12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758Copyright © 2010 Marvell PUBLIC RELEASE Doc. No. MV-S301208-00 Rev. -Page 41
Page 1 and 2: CoverMarvell® PXA3xx Processors an
Page 3 and 4: Table of Contents1 Boot ROM Functio
Page 5 and 6: 6.3.5 USB Vendor Request Package ..
Page 7 and 8: Figure 1:PXA3xx Top Level Boot ROM
Page 9 and 10: Table 42: Host Commands ...........
Page 11 and 12: 1 Boot ROM Functional Overview1.1 G
Page 13 and 14: Figure 1:PXA3xx Top Level Boot ROM
Page 15 and 16: Boot ROM Differences2 Boot ROM Diff
Page 17 and 18: Boot ROM DifferencesTIM/NTIM/OBM Su
Page 19 and 20: Boot ROM DifferencesPXA31x and Tavo
Page 21 and 22: Boot ROM DifferencesPXA31x and Tavo
Page 23 and 24: 3 Software RequirementsThis chapter
Page 25 and 26: Typedef struct S_Reloc{USHORT Heade
Page 27 and 28: 4 Methods for Platform Provisioning
Page 29 and 30: 4. If the same OEM boot module is u
Page 31 and 32: multiple versions of the Device Key
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PXA3xx Processors and Tavor Process
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Marvell Semiconductor, Inc.700 Firs
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PXA3xx Boot ROM Reference Manual - Marvell

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