Data Acquisition

The next few sections describe the actual timing relationships of the signals on the bus forthe various types of bus cycles.These are:• Memory-read: data transfer from a memory device to the CPU• Memory-write: data transfer from the CPU to a memory device• I/O-read: data transfer from an I/O device to the CPU• I/O-write: data transfer from the CPU to an I/O device• DMA Write I/O: data transfer from a memory device to an I/O device• DMA Read I/O: data transfer from an I/O device to a memory deviceMemory-read and memory-write cycles are essentially similar and are discussed together,as are I/O-read and I/O-write cycles and the two different directions of DMA cycles.A further type of cycle run on the system board is the interrupt acknowledge cycle. It is notpresent on the expansion bus and therefore not relevant to expansion board design.Lastly, there may be cycles on the bus, run by bus master boards.The timing of these cycles obviously depends on the bus master board, but the initiationand conclusion (i.e. the bus arbitration) of bus master cycles have fixed timing specifications.This is not discussed here but guidelines were given in the previous section on bus signal descriptions.In the timing charts that follow, dots are used to indicate sampling points and shaded areasindicate a ‘don’t care’ state.Memory-read and memory-write cyclesThe following three timing charts show instances of 8-bit memory access:• A standard 6-BCLK cycle• A cycle which the expansion board extends (to seven BCLKs) with CHRDY• A cycle shortened by the expansion board to three BCLKs with the /NOWS signalAs all the I/O bus cycles described here are fairly similar in mechanism, the firstdescription below applies to all of them; the individual cycle descriptions that follow focus onadditional details as well as on points of difference with the general description.Standard 6-BCLK 8-bit memory accessFigure 4.5 shows the XT-compatible cycle, which is the default for I/O memory access in theabsence of intervention by an expansion board. It consists of a T S state, the send status state,followed by four wait states inserted by the system board, followed by the perform commandstate, (T C ).In the standard memory cycle, BALE goes active in the last half of T S . It indicates a validaddress on the latchable address lines LA[23..17], and its trailing edge may be used to latchthese addresses if they are required by the expansion board for the remainder of the cycle.Note that LA[23..17] are valid before the machine cycle begins and go invalid in the latterhalf of the state following T S . This allows them to be setup before the next machine cyclebegins, and is called address pipelining. (On the EISA bus, all the address lines from A2 toA32 are available in latchable form, which allows more flexible shortening of the bus cycle.)Compare this to the address lines SA[19..0], which go valid just before the second machinestate begins and remain valid throughout the remainder of the machine cycle (and a little intothe next). The address lines are used to decode the address(es) of the device(s) on the expansionboard.