Data Acquisition

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field or if the field is caused by currents flowing through nearby pairs of wires, twist-ingthose wires to reduce the net magnetic field effect to zero and or by alternating itsdirection.The signal circuit loop area (A) can be reduced by placing the signal wires of thereceiving circuit current loop closer together. For example, consider a signal circuitwhose current carrying wires are 1 meter long and 1 centimeter apart, lying within a 10gauss 60 Hz magnetic field, typical of fans, power wiring and transformers. The maximumvoltage induced in the wires occurs for φ = 0º.V n = (2π × 60)(1)(1 × 10 –2 )(10 –4 ) = 3.7 mV.If the distance between the wires is reduced to 1 mm the noise voltage is reducedtenfold to 0.37 mV.The cosφ, term can be reduced by correctly orienting the wires of the signal circuit inthe magnetic field. For example, if the signal wires were perpendicular to the magneticfield (φ = 90°) the induced voltage could be reduced to zero, although practically thiswould not be possible. Running the signal wires together in the same cable as the wirescarrying the noise current source would maximize the induced noise voltage.The equivalent circuit model of magnetic coupling between a noise source and a signalcircuit is shown in Figure 3.34. In terms of the mutual inductance (M), V n is given by:V n = 2 π f M I NI N is the rms value of the sinusoidal current in the noise circuit and f is its frequency. Themutual inductance (M) is directly proportional to the area (A) of the signal circuit currentloop and the flux density, (B).The physical geometry of the current loop of the receiving signal circuit, specifically itsarea, is the key to why it is susceptible to magnetic fields and how to minimize the effect.Cables provide the longest and largest current loop. The effect of magnetic coupling isbest demonstrated by considering the circuit of Figure 3.34, in which the signal cablecurrent loop is coupled by a sinusoidal changing magnetic field with a peak flux densityof Bφ.Figure 3.34Equivalent circuit model of magnetic coupling between a noise source and a signal circuitIdeally, the only voltage appearing across the load should be V S – the source signalvoltage. However, the magnetic flux induces a voltage in the loop that appears in serieswith the receiver signal circuit. The voltage appearing across the load is the sum of thesource voltage and the unwanted magnetic field induced voltage (V N ).Twisting the insulated conductors of the loop together, as shown in Figure 3.35, cangreatly reduce the amount of magnetic coupling into the signal lines.
Figure 3.35Reducing magnetic noise coupling by twisting of wiresThe voltage induced in each section of the loop now alternates phases; its magnitudereduced by the reduction in area of each twisted loop (i.e. 1/4). Provided there is an evennumber of twists in the signal conductors, the voltages due to the magnetic field cancelout and only the desired signal voltage appears across the load.3.6.1 Cable shielding and shield earthingThe effects of noise due to capacitive coupling can be greatly reduced by the use of acylindrical metal shield placed around the signal-carrying conductor. Consider theequivalent circuit shown in Figure 3.36, in which the signal conductors are completelyenclosed by the ungrounded shield.Figure 3.36Equivalent representation of a signal circuit, completely surrounded by a capacitive shieldNote that as the signal conductors are completely enclosed, there is no stray capacitancebetween the signal conductors and ground.Where the source resistance (R S ) is much less than the load resistance (R L ) and alsomuch lower than the impedance of the shield to signal conductor stray capacitance (C 2S ),(i.e. R S
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Practical Data Acquisition forInstr
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Practical Data Acquisition forInstr
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In less than a decade, the PC has b
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PrefaceContentsxvii1 Introduction 1
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Contents vii4.2.1 Hardware interrup
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Contents ix6.2.3 Functional descrip
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Contents xi9.1 Ethernet and fieldbu
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Contents xiii12.5.2 Pin assignments
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Contents xvType R thermocouple 384T
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A data acquisition and control syst
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FilteringIn noisy environments, it
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are capable of programmed I/O and i
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Plug-in expansion boards are common
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Page 32 and 33: 14 Practical Data Acquisition for I
Page 54 and 55: 3PC based data acquisition (DAQ) sy
Page 56 and 57: 3.2.3 FilteringIsolation performs s
Page 58 and 59: The transfer characteristics of a p
Page 60 and 61: Figure 3.7Ideal band pass filter tr
Page 62 and 63: Figure 3.11Two-stage Butterworth fi
Page 64 and 65: As individual signal conditioning m
Page 66 and 67: ThermocouplesDigitalTransmitterDigi
Page 68 and 69: Examples of floating signal sources
Page 70 and 71: espect to the measurement system gr
Page 72 and 73: Figure 3.26Opto-coupler isolation o
Page 74 and 75: • Using isolation amplifiers to i
Page 76 and 77: Figure 3.31Physical representation
Page 80 and 81: Where the shield is grounded (i.e.
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Page 84 and 85: For full-duplex systems using balan
Page 86 and 87: 4.1.1 DOSusually consist of a small
Page 88 and 89: With the advent of Windows as a gra
Page 90 and 91: UNIX shellSimilar to the DOS comman
Page 92 and 93: available to the expansion bus. A l
Page 94 and 95: 4.2.7 Interrupt service routinesIt
Page 96 and 97: Whichever CPU is being used, it mus
Page 98 and 99: • An I/O device requests a DMA tr
Page 100 and 101: Normal DMA using on-board FIFOThe D
Page 102 and 103: ferring samples until the counter r
Page 104 and 105: The read or write command signals (
Page 106 and 107: Shortened 3-BCLK 8-bit memory acces
Page 108 and 109: Extended 6-BCLK 16-bit memory acces
Page 110 and 111: • A cycle which the expansion boa
Page 112 and 113: Figure 4.13Timing chart of a shorte
Page 114 and 115: Figure 4.15Timing chart of an exten
Page 116 and 117: 4.7.2 Expanded memory system (EMS)E
Page 118 and 119: The IBM PC and early versions of th
Page 120 and 121: Figure 4.17ISA signal mnemonics, si
Page 122 and 123: data bus. An example of this happen
Page 124 and 125: NOWSThe /NOWS (NO wait state) signa
Page 126 and 127: interrupt lines (1RQ13, 8, 2, 1 and
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one application at a time, it is ne
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The need for PCs to exchange data w
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Figure 4.198-bit 21-line I/O board4
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Address decoding on the 24-line pro
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The write cycle is considered in th
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data acquisition and control system
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Adjustable on-board fixed gain ampl
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level applied at the input. When a
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Each step effectively divides the r
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The operation of a dual slope integ
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Code widthThis is the fundamental q
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(a) Unipolar offset error(b) Bipola
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Changes in temperature result in a
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1 LSB. Therefore, an ideal A/D conv
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• The source and level of interru
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5.3.3 Differential inputsTrue diffe
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A/D board can divide the input rang
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a) DC alias caused by sampling at h
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Figure 5.15Frequency spectrum of or
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ate be a minimum of about five time
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Figure 5.20Many aliases combined wi
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initiated. The data is subsequently
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Figure 5.22Time skew between channe
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For each burst trigger, the A/D boa
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Analog output D/A boardsUnlike high
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Like the weighted-current source ne
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The generation of high frequency si
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• The plug-in connector, which pr
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Latched digital I/OFor applications
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y increasing the resistance of R x
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One advantage of this type of relay
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Figure 5.36Waveforms showing genera
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When a counter is configured to ena
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6The standardization of the RS-232
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A duplex system is designed for sen
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Some examples of the HEX and BIN va
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In summary, the optional settings f
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At the RS-232 receiver the followin
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110 850300 800600 7001200 5002400 2
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• Pin 7: Signal ground (common)Th
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6.2.5 Examples of RS-232 interfaces
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terminating resistors, approximatel
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Another commonly used technique, ba
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• Line controlThis applies to hal
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The calculation of the block checks
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The mechanism of operation of the C
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Figure 6.18, has appropriate intern
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77.1 IntroductionAs with other form
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inserted in the device. This is its
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How frequently logged data is uploa
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The following hardware components d
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In a typical stand-alone data acqui
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The maximum battery life that can b
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Input termination resistors, typica
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Figure 7.13 shows the standard conn
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interface, even at high speed, the
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• Use different data formats so t
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Command errors are reported immedia
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• Channel scalingThis automatical
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The channel scan for this type of s
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Data is logged in a fixed non-ASCII
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7.9 Stand-alone logger/controllers
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88.1 IntroductionThe communications
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Figure 8.2GPIB connector (IEEE 488)
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• TalkersA talker is a one-way co
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controller in charge (CIC). The IFC
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Each device connected to the GPIB h
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One of the additional features that
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• The controller temporarily conf
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Table 8.4IEEE 488.2 commandsThe SCP
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Figure 8.9SCPI instrument modelThe
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99.1 Ethernet and fieldbuses for da
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cabling tray etc and the transceive
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transceiver in the MAU and this is
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Advantages of the system include:
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of a cell as well, but these are ig
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Figure 9.8CSMA/CD collisionsAssume
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• PreambleThis field consists of
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of this figure. Some manufacturers
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Grounding has safety and noise conn
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Just as with any technology, each o
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information. The packet is then pla
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There are two types of connectors,
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HOSTClient SoftwareManages Interfac
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Figure 10.6USB connector pinsThere
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The idle states for low- and high-s
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The interrupt transfer type is used
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than in spending a lot of time and
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• The sensitivity of the output/i
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term error (m) in the system and ad
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11.2 Capturing high speed transient
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12IntroductionThe PCMCIA (PCMCIA st
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adapter on a full size computer has
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Pager cards are used in offices and
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Size 85.6 mm × 54.0 mmType I 3.3 m
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The memory only interface is conver
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The AIMS interface supports large d
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12.8 FutureThe card information str
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A/D conversion timeAddressAddress r
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Back-planeBand pass filterBandwidth
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BufferBusBWCache memoryCCDCCIRCCITT
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pixel is subjected to a mathematica
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data between the computer memory an
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FrameFrame grabberFringingFull dupl
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so that they interlock. The PAL sta
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Lux-secondSI unit of light exposure
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NTSCNull modemNumber of channelsNyq
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PortPPIPre-triggerProgram I/OProgra
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whereby the first gray level of eac
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allowing the user to control basic
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input.TrunkUARTUnipolar inputsUnloa
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Appendix BThe information in this s
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Table B.4Controller 2: 16-bit (AT o
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B.5 8253/8254 Counter/timer
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Table B.8Memory map for PC/XT/AT
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Table B.10BIOS data area
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Table B.15ROMTable B.16AT extended
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← ↔ ← ← ← ↔
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Figure B.1Card dimensions for PC/XT
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Appendix CThis section contains bri
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the control register of the 8255. T
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The bits A7 (MSB) down to A0 (LSB)
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Table C.6Instructions for reading o
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The program could also enable the I
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Group AConfiguration Informationto
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C.11 Single-bit set/resetAny of the
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Figure C.15Bi-directional bus (mode
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Figure D.18254 Block diagramFigure
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Figure D.3TCCTRL registerThe functi
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This is the data register of the fi
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• A simple read operation• A co
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The null count bit indicates if the
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For even counts: the output is init
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Appendix EThe IPTS-68 standard defi
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Number of ranges = 2Range #1 -270 t
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Range #2 0 to 1372°COrder of polyn
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Number of Ranges = 4Range #1 -50 to
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Appendix FF.1 IntroductionAll activ
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Table F.3 gives the conversion betw
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The conversion between binary and h
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F.8 Internal representation of info
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12 which is equivalent to: 1100-4 S
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DCDCASDCISDCLDDDIODTDTASDTISENDEOIE
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STBSTRSSWNST(T)TETACSTADSTAGTCATCST
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404 IndexDuplex:full duplex 178half
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406 IndexOpen loop control 285see a
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THIS BOOK WAS DEVELOPED BY IDC TECH
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