Data Acquisition

data bus. An example of this happens when the expansion board had previously indicated tothe system board that it is capable of transferring 16-bit data with the /IO16 or /M16 signals.The type of bus cycle can be decoded from /SBHE and SA0 as follows: Table 4.4Decoding bus cycle type from /SBHE and SA0AENWhen low, AEN (address enable) indicates that an I/O slave may respond to addresses andI/O commands on the bus. It is an output signal issued by the DMA control logic duringDMA cycles which, when asserted (high), is used to prevent I/O slaves from misinterpretingDMA cycles as I/O cycles. The system board also uses this signal to disable the processor’saddress, data, and control lines from the I/O bus during DMA cycles.Data transfer control signal groupThis group contains signals that are used to control data transfer cycles on the bus.BCLKBCLK (bus clock) is provided to synchronize events with the main system clock. Accordingto EISA specifications, BCLK should operate at a frequency between 8.333 MHz and 4 MHz,with a normal duty cycle of 50%. However, most ISA systems have a BCLK frequency of8 MHz to 12 MHz. (The original XT had a high time of 66⅔% and a low time of 33⅓% and afrequency of 4.77 MHz.) BCLK is driven by the system board. Its period is sometimesextended for synchronization to the main CPU or other system board devices. During busmaster cycles, the system board extends BCLK only when required to synchronize with mainmemory. Events must be synchronized to BCLK edges without regard to frequency or dutycycle. This signal can be used to generate system bus wait states.BALEWhen high, BALE (address latch enable) indicates that a valid address is present on thelatchable address lines LA17 to LA23. It goes high before the addresses are valid and fallslow after they have become valid. If the addresses are needed for the whole cycle, theexpansion board should latch them with the trailing edge of BALE. This is a goodsynchronization signal when looking at normal bus cycles because it starts at the beginning ofeach bus cycle. It is high (and does not fall low) during DMA or bus master cycles./MRDCThis signal is asserted by the system board or ISA bus master to indicate that the addressedmemory slave should drive its data onto the system data bus. This should be done before therising edge of the /MRDC signal to ensure that the receiving device obtains valid data.