Data Acquisition

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For example, to convert decimal number 43 10 to binary form:Table F.4Illustration of decimal to binary conversionThis translates a number 43 10 to 101011 2F.4 Hexadecimal numbersMost of the work done with computers and data communications systems is based on theHexadecimal number system, as it is easy to translate a binary number into a hexadecimalequivalent. This has a base of 16 and uses the sequence of symbols:0, l, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, FHence the number of FA9.02 16 would be represented as below in Table F.5: Table F.5Hexadecimal weighting structureThis translates into the following number:0 × 16 4 + 0 × 16 3 +F × 16 2 +A × 16 1 +0 × 16 -1 +0 × 16 -2 + ……..= 15 × 16 2 + 10 × 16 1 + 9 × 1+ 2 × 1/16 2= 15 × 256 + 10 × 16+ 9 × 1+ 2 /256= 4009.0078125The most significant digit (MSD) in the above number is the left most symbol and is Fwith weighting of 16 2 . The right most symbol is the least significant digit (LSD) and isvalued at 2 with a weighting of 16 –2 .
The conversion between binary and hexadecimal is effected by modifying Table F.3 tothe table following:F.5 Octal Table F.6Relationship between decimal, binary, and hexadecimal numbersAs can be seen from the table, the binary numbers are grouped in fours for the largestsingle digit hexadecimal character or symbol. A similar approach, of grouping bits infours, is followed in expressing a binary number as a hexadecimal number.In converting the binary number 1000010011110111 2 to its hexadecimal equivalent, thefollowing procedure should be adopted. First, break up the binary number into groups offour commencing from the least significant bit. Then equate the equivalent hex symbol toit (derived from Table F.6 above).1000010011110111 becomes:1000 … 0100 … 1111 … 0111 28 4 F 7 16Or 8 4 F 7 16In order to convert a hexadecimal number back to binary the procedure used abovemust be reversed.For example, in converting from C9A4 to binary this becomes:C ... 9 ... A ... 4 161100 … 1001 ... 1010 ... 0100 2Or 1100100110100100 2Some of the older computer systems used octal for their coding. This uses the sequence ofsymbols:
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Practical Data Acquisition forInstr
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Practical Data Acquisition forInstr
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In less than a decade, the PC has b
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PrefaceContentsxvii1 Introduction 1
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Contents vii4.2.1 Hardware interrup
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Contents ix6.2.3 Functional descrip
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Contents xi9.1 Ethernet and fieldbu
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Contents xiii12.5.2 Pin assignments
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Contents xvType R thermocouple 384T
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A data acquisition and control syst
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FilteringIn noisy environments, it
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are capable of programmed I/O and i
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Plug-in expansion boards are common
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50 mRS-232 Communication InterfaceS
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speeds are of the order of 1 Mbyte/
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14 Practical Data Acquisition for I
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3PC based data acquisition (DAQ) sy
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3.2.3 FilteringIsolation performs s
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The transfer characteristics of a p
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Figure 3.7Ideal band pass filter tr
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Figure 3.11Two-stage Butterworth fi
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As individual signal conditioning m
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ThermocouplesDigitalTransmitterDigi
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Examples of floating signal sources
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espect to the measurement system gr
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Figure 3.26Opto-coupler isolation o
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• Using isolation amplifiers to i
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Figure 3.31Physical representation
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field or if the field is caused by
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Where the shield is grounded (i.e.
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mines the amount of noise in the ci
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For full-duplex systems using balan
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4.1.1 DOSusually consist of a small
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With the advent of Windows as a gra
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UNIX shellSimilar to the DOS comman
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available to the expansion bus. A l
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4.2.7 Interrupt service routinesIt
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Whichever CPU is being used, it mus
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• An I/O device requests a DMA tr
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Normal DMA using on-board FIFOThe D
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ferring samples until the counter r
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The read or write command signals (
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Shortened 3-BCLK 8-bit memory acces
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Extended 6-BCLK 16-bit memory acces
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• A cycle which the expansion boa
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Figure 4.13Timing chart of a shorte
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Figure 4.15Timing chart of an exten
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4.7.2 Expanded memory system (EMS)E
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The IBM PC and early versions of th
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Figure 4.17ISA signal mnemonics, si
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data bus. An example of this happen
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NOWSThe /NOWS (NO wait state) signa
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interrupt lines (1RQ13, 8, 2, 1 and
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one application at a time, it is ne
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The need for PCs to exchange data w
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Figure 4.198-bit 21-line I/O board4
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Address decoding on the 24-line pro
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The write cycle is considered in th
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data acquisition and control system
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Adjustable on-board fixed gain ampl
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level applied at the input. When a
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Each step effectively divides the r
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The operation of a dual slope integ
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Code widthThis is the fundamental q
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(a) Unipolar offset error(b) Bipola
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Changes in temperature result in a
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1 LSB. Therefore, an ideal A/D conv
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• The source and level of interru
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5.3.3 Differential inputsTrue diffe
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A/D board can divide the input rang
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a) DC alias caused by sampling at h
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Figure 5.15Frequency spectrum of or
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ate be a minimum of about five time
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Figure 5.20Many aliases combined wi
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initiated. The data is subsequently
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Figure 5.22Time skew between channe
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For each burst trigger, the A/D boa
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Analog output D/A boardsUnlike high
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Like the weighted-current source ne
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The generation of high frequency si
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• The plug-in connector, which pr
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Latched digital I/OFor applications
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y increasing the resistance of R x
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One advantage of this type of relay
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Figure 5.36Waveforms showing genera
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When a counter is configured to ena
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6The standardization of the RS-232
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A duplex system is designed for sen
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Some examples of the HEX and BIN va
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In summary, the optional settings f
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At the RS-232 receiver the followin
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110 850300 800600 7001200 5002400 2
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• Pin 7: Signal ground (common)Th
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6.2.5 Examples of RS-232 interfaces
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terminating resistors, approximatel
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Another commonly used technique, ba
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• Line controlThis applies to hal
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The calculation of the block checks
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The mechanism of operation of the C
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Figure 6.18, has appropriate intern
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77.1 IntroductionAs with other form
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inserted in the device. This is its
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How frequently logged data is uploa
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The following hardware components d
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In a typical stand-alone data acqui
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The maximum battery life that can b
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Input termination resistors, typica
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Figure 7.13 shows the standard conn
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interface, even at high speed, the
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• Use different data formats so t
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Command errors are reported immedia
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• Channel scalingThis automatical
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The channel scan for this type of s
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Data is logged in a fixed non-ASCII
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7.9 Stand-alone logger/controllers
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88.1 IntroductionThe communications
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Figure 8.2GPIB connector (IEEE 488)
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• TalkersA talker is a one-way co
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controller in charge (CIC). The IFC
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Each device connected to the GPIB h
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One of the additional features that
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• The controller temporarily conf
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Table 8.4IEEE 488.2 commandsThe SCP
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Figure 8.9SCPI instrument modelThe
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99.1 Ethernet and fieldbuses for da
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cabling tray etc and the transceive
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transceiver in the MAU and this is
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Advantages of the system include:
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of a cell as well, but these are ig
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Figure 9.8CSMA/CD collisionsAssume
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• PreambleThis field consists of
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of this figure. Some manufacturers
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Grounding has safety and noise conn
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Just as with any technology, each o
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information. The packet is then pla
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There are two types of connectors,
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HOSTClient SoftwareManages Interfac
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Figure 10.6USB connector pinsThere
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The idle states for low- and high-s
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The interrupt transfer type is used
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than in spending a lot of time and
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• The sensitivity of the output/i
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term error (m) in the system and ad
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11.2 Capturing high speed transient
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12IntroductionThe PCMCIA (PCMCIA st
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adapter on a full size computer has
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Pager cards are used in offices and
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Size 85.6 mm × 54.0 mmType I 3.3 m
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The memory only interface is conver
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The AIMS interface supports large d
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12.8 FutureThe card information str
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A/D conversion timeAddressAddress r
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Back-planeBand pass filterBandwidth
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BufferBusBWCache memoryCCDCCIRCCITT
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pixel is subjected to a mathematica
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data between the computer memory an
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FrameFrame grabberFringingFull dupl
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so that they interlock. The PAL sta
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Lux-secondSI unit of light exposure
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NTSCNull modemNumber of channelsNyq
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PortPPIPre-triggerProgram I/OProgra
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whereby the first gray level of eac
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allowing the user to control basic
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input.TrunkUARTUnipolar inputsUnloa
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Appendix BThe information in this s
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Table B.4Controller 2: 16-bit (AT o
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B.5 8253/8254 Counter/timer
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Table B.8Memory map for PC/XT/AT
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Page 361 and 362: Table B.15ROMTable B.16AT extended
Page 363 and 364: ← ↔ ← ← ← ↔
Page 365 and 366: Figure B.1Card dimensions for PC/XT
Page 367 and 368: Appendix CThis section contains bri
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Page 371 and 372: The bits A7 (MSB) down to A0 (LSB)
Page 373 and 374: Table C.6Instructions for reading o
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Page 377 and 378: Group AConfiguration Informationto
Page 379 and 380: C.11 Single-bit set/resetAny of the
Page 381 and 382: Figure C.15Bi-directional bus (mode
Page 383 and 384: Figure D.18254 Block diagramFigure
Page 385 and 386: Figure D.3TCCTRL registerThe functi
Page 387 and 388: This is the data register of the fi
Page 389 and 390: • A simple read operation• A co
Page 391 and 392: The null count bit indicates if the
Page 393 and 394: For even counts: the output is init
Page 395 and 396: Appendix EThe IPTS-68 standard defi
Page 397 and 398: Number of ranges = 2Range #1 -270 t
Page 401 and 402: Range #2 0 to 1372°COrder of polyn
Page 403 and 404: Number of Ranges = 4Range #1 -50 to
Page 407 and 408: Appendix FF.1 IntroductionAll activ
Page 409: Table F.3 gives the conversion betw
Page 413 and 414: F.8 Internal representation of info
Page 415 and 416: 12 which is equivalent to: 1100-4 S
Page 417 and 418: DCDCASDCISDCLDDDIODTDTASDTISENDEOIE
Page 419 and 420: STBSTRSSWNST(T)TETACSTADSTAGTCATCST
Page 421 and 422: 404 IndexDuplex:full duplex 178half
Page 423 and 424: 406 IndexOpen loop control 285see a
Page 425: THIS BOOK WAS DEVELOPED BY IDC TECH
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Data Acquisition

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