Data Acquisition

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Figure 8.2GPIB connector (IEEE 488) and pin assignmentsThe 24 lines, in each cable, consist of 8 data lines and 8 pairs (16) of control and busmanagement lines. The data lines are used exclusively to carry data, in a parallel configuration,one byte at a time, along the bus. The control and bus management lines areused for various bus management tasks that synchronize the flow of data. When data orcommands are sent down the bus, the bus management lines distinguish between the two.The GPIB uses binary voltage signals to represent the information that is carried on thelines of the bus. It uses the symbols ‘true’ and ‘false’ to represent the two states ofvoltages on the lines. The GPIB uses the logic convention called ‘low-true’ or negativelogic, where the lower voltage state is ‘true’ and the higher voltage state is ‘false’.Standard TTL voltage levels are used. For example, when a line is true, or asserted, theTTL voltage level is low (≤ 0.8 V), and when the line is ‘false’, or unasserted, the TTLlevel is high (≥ 2.0V). The ‘low-true’ logic means that any device can set a bus controlvoltage ‘low-true’, but no line can be at a voltage ‘high=false’ unless all the devices onthat line allow it to go ‘high=false’.8.3 Physical connection configurationsThe devices on the GPIB can be connected in a star configuration, as shown in Figure 8.3,or in a chain (linear) configuration as shown in Figure 8.4.A star configuration is one where each instrument is connected, by means of a separateGPIB cable, directly to the controller. The connectors are all connected to the same portat the controller. A drawback to this simple configuration is that all of the devices on thebus must be relatively close to the controller because of the length limitation of eachcable.
InstrumentAGPIB controllerHost ComputerInstrumentBInstrumentCFigure 8.3The GPIB star configurationIn the chain configuration, each device, including the controller, is connected to the nextin a chain. The controller does not have to be the first or last device in the chain, but canbe linked in anywhere. It is a controller only in the sense that it co-ordinates the events onthe bus. Physically and electrically, it is similar to any other device connected to theGPIB. This configuration is usually the most convenient way to connect equipment. Adisadvantage of the chain configuration is that the software may require reconfiguration ifa device and its cable are removed.GPIB controllerHost ComputerInstrumentAInstrumentBInstrumentCFigure 8.4The GPIB chain (linear) configurationAlthough the star and chain configurations are suggested for GPIB, connections can bemade in any other way, provided that the following rules are observed:• All devices are connected to the bus• No more than 15 devices, including the controller, may be on the bus, with noless than two thirds powered on• Cable length between any two devices may not exceed 4 meters with anaverage separation of 2 meters over the entire bus• Total cable length may not exceed 20 metersA single device on the GPIB can transfer data up to 14 other devices. Because the GPIBuses asynchronous (un-clocked) handshaking, the actual data transfer rate is moredependent on the devices themselves rather than on the hardware interface.8.4 Device typesFrom a data communications standpoint, there are four different groups of devices thatcommunicate on a GPIB interface:
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Practical Data Acquisition forInstr
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Practical Data Acquisition forInstr
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In less than a decade, the PC has b
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PrefaceContentsxvii1 Introduction 1
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Contents vii4.2.1 Hardware interrup
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Contents ix6.2.3 Functional descrip
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Contents xi9.1 Ethernet and fieldbu
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Contents xiii12.5.2 Pin assignments
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Contents xvType R thermocouple 384T
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A data acquisition and control syst
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FilteringIn noisy environments, it
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are capable of programmed I/O and i
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Plug-in expansion boards are common
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50 mRS-232 Communication InterfaceS
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speeds are of the order of 1 Mbyte/
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14 Practical Data Acquisition for I
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3PC based data acquisition (DAQ) sy
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3.2.3 FilteringIsolation performs s
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The transfer characteristics of a p
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Figure 3.7Ideal band pass filter tr
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Figure 3.11Two-stage Butterworth fi
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As individual signal conditioning m
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ThermocouplesDigitalTransmitterDigi
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Examples of floating signal sources
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espect to the measurement system gr
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Figure 3.26Opto-coupler isolation o
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• Using isolation amplifiers to i
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Figure 3.31Physical representation
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field or if the field is caused by
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Where the shield is grounded (i.e.
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mines the amount of noise in the ci
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For full-duplex systems using balan
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4.1.1 DOSusually consist of a small
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With the advent of Windows as a gra
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UNIX shellSimilar to the DOS comman
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available to the expansion bus. A l
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4.2.7 Interrupt service routinesIt
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Whichever CPU is being used, it mus
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• An I/O device requests a DMA tr
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Normal DMA using on-board FIFOThe D
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ferring samples until the counter r
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The read or write command signals (
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Shortened 3-BCLK 8-bit memory acces
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Extended 6-BCLK 16-bit memory acces
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• A cycle which the expansion boa
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Figure 4.13Timing chart of a shorte
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Figure 4.15Timing chart of an exten
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4.7.2 Expanded memory system (EMS)E
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The IBM PC and early versions of th
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Figure 4.17ISA signal mnemonics, si
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data bus. An example of this happen
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NOWSThe /NOWS (NO wait state) signa
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interrupt lines (1RQ13, 8, 2, 1 and
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one application at a time, it is ne
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The need for PCs to exchange data w
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Figure 4.198-bit 21-line I/O board4
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Address decoding on the 24-line pro
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The write cycle is considered in th
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data acquisition and control system
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Adjustable on-board fixed gain ampl
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level applied at the input. When a
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Each step effectively divides the r
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The operation of a dual slope integ
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Code widthThis is the fundamental q
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(a) Unipolar offset error(b) Bipola
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Changes in temperature result in a
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1 LSB. Therefore, an ideal A/D conv
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• The source and level of interru
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5.3.3 Differential inputsTrue diffe
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A/D board can divide the input rang
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a) DC alias caused by sampling at h
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Figure 5.15Frequency spectrum of or
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ate be a minimum of about five time
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Figure 5.20Many aliases combined wi
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initiated. The data is subsequently
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Figure 5.22Time skew between channe
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For each burst trigger, the A/D boa
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Analog output D/A boardsUnlike high
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Like the weighted-current source ne
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The generation of high frequency si
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• The plug-in connector, which pr
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Latched digital I/OFor applications
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y increasing the resistance of R x
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One advantage of this type of relay
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Figure 5.36Waveforms showing genera
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When a counter is configured to ena
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6The standardization of the RS-232
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A duplex system is designed for sen
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Some examples of the HEX and BIN va
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In summary, the optional settings f
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At the RS-232 receiver the followin
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Page 216 and 217: The calculation of the block checks
Page 218 and 219: The mechanism of operation of the C
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Page 222 and 223: 77.1 IntroductionAs with other form
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Page 228 and 229: The following hardware components d
Page 230 and 231: In a typical stand-alone data acqui
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Page 236 and 237: Figure 7.13 shows the standard conn
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Page 240 and 241: • Use different data formats so t
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Page 244 and 245: • Channel scalingThis automatical
Page 246 and 247: The channel scan for this type of s
Page 248 and 249: Data is logged in a fixed non-ASCII
Page 250 and 251: 7.9 Stand-alone logger/controllers
Page 252 and 253: 88.1 IntroductionThe communications
Page 256 and 257: • TalkersA talker is a one-way co
Page 258 and 259: controller in charge (CIC). The IFC
Page 260 and 261: Each device connected to the GPIB h
Page 262 and 263: One of the additional features that
Page 264 and 265: • The controller temporarily conf
Page 266 and 267: Table 8.4IEEE 488.2 commandsThe SCP
Page 268 and 269: Figure 8.9SCPI instrument modelThe
Page 270 and 271: 99.1 Ethernet and fieldbuses for da
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Page 280 and 281: Figure 9.8CSMA/CD collisionsAssume
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Page 288 and 289: Just as with any technology, each o
Page 290 and 291: information. The packet is then pla
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Page 294 and 295: HOSTClient SoftwareManages Interfac
Page 296 and 297: Figure 10.6USB connector pinsThere
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• The sensitivity of the output/i
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term error (m) in the system and ad
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11.2 Capturing high speed transient
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12IntroductionThe PCMCIA (PCMCIA st
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adapter on a full size computer has
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Pager cards are used in offices and
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Size 85.6 mm × 54.0 mmType I 3.3 m
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The memory only interface is conver
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The AIMS interface supports large d
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12.8 FutureThe card information str
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A/D conversion timeAddressAddress r
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Back-planeBand pass filterBandwidth
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BufferBusBWCache memoryCCDCCIRCCITT
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pixel is subjected to a mathematica
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data between the computer memory an
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FrameFrame grabberFringingFull dupl
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so that they interlock. The PAL sta
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Lux-secondSI unit of light exposure
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NTSCNull modemNumber of channelsNyq
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PortPPIPre-triggerProgram I/OProgra
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whereby the first gray level of eac
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allowing the user to control basic
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input.TrunkUARTUnipolar inputsUnloa
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Appendix BThe information in this s
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Table B.4Controller 2: 16-bit (AT o
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B.5 8253/8254 Counter/timer
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Table B.8Memory map for PC/XT/AT
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Table B.10BIOS data area
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Table B.15ROMTable B.16AT extended
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← ↔ ← ← ← ↔
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Figure B.1Card dimensions for PC/XT
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Appendix CThis section contains bri
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the control register of the 8255. T
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The bits A7 (MSB) down to A0 (LSB)
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Table C.6Instructions for reading o
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The program could also enable the I
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Group AConfiguration Informationto
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C.11 Single-bit set/resetAny of the
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Figure C.15Bi-directional bus (mode
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Figure D.18254 Block diagramFigure
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Figure D.3TCCTRL registerThe functi
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This is the data register of the fi
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• A simple read operation• A co
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The null count bit indicates if the
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For even counts: the output is init
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Appendix EThe IPTS-68 standard defi
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Number of ranges = 2Range #1 -270 t
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Range #2 0 to 1372°COrder of polyn
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Number of Ranges = 4Range #1 -50 to
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Appendix FF.1 IntroductionAll activ
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Table F.3 gives the conversion betw
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The conversion between binary and h
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F.8 Internal representation of info
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12 which is equivalent to: 1100-4 S
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DCDCASDCISDCLDDDIODTDTASDTISENDEOIE
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STBSTRSSWNST(T)TETACSTADSTAGTCATCST
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404 IndexDuplex:full duplex 178half
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406 IndexOpen loop control 285see a
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THIS BOOK WAS DEVELOPED BY IDC TECH
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Data Acquisition

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