Data Acquisition

Figure 4.1IRQ4.2.1 Hardware interruptsTwo types of hardware interrupt are available, non-maskable interrupts (NMI) and the maskableinterrupt (INTR), connected respectively to the NMI and INTR input pins of the CPU.4.2.2 Non-maskable interruptsSince NMIs are not maskable internally in the CPU, logic on the system board uses an I/Oregister port (A0h) bit to mask and unmask the NMI.The CPU’s NMI interrupt input is transition-sensitive or edge-sensitive with a low to hightransition triggering the interrupt. It is used to indicate to the CPU serious conditions, such assystem RAM parity errors or impending power failure.NMIs can also occur when the bus expansion signal /IOCHK (I/O channel check) isasserted low, bit 3 of Port 61h is cleared and NMIs are enabled with port A0h. The /IOCHKsignal is used by I/O devices to indicate that a serious error such as a memory parity error oran uncorrectable hardware fault has occurred on their expansion board.When the CPU receives an NMI, it automatically begins executing the code pointed to byinterrupt vector 2 (i.e. a type 2 interrupt is generated).4.2.3 Maskable interruptsThe CPU recognizes a hardware maskable interrupt when its INTR input goes from low tohigh with the interrupt enabled. INTR interrupts are enabled/disabled by setting/clearing theinterrupt enable flag bit IF in the CPU FLAGS register.4.2.4 Programmable interrupt controller(s)As there is only one maskable hardware interrupt line (INTR) and many I/O devices whichmust inform the CPU that they require servicing (by generating interrupts), there needs to bea method of prioritizing the PC’s interrupt structure for more than just one interrupt. This taskis performed by the 8259A programmable interrupt controller (PIC), which accepts interruptrequests from I/O devices, prioritizes and stores them, and generates the interrupt requestsignal (INTR) to the CPU as required.The PC/XT has only one 8259A PIC with interrupts IRQ0 to IRQ7, whilst the 80286/80386and 80486-based PCs have two 8259As. The output of the second (or slave PIC) 8259A isconnected directly to the IRQ2 channel of the master PIC.Hardware interrupt requests by I/O devices are made on the interrupt lines IRQ (15..14),IRQ (12..9), IRQ (7..3). IRQ 0,1,2, 8 and 13 are used by the system board and are not