Data Acquisition

NOWSThe /NOWS (NO wait state) signal may be driven by a memory device after it has decodedits address and command to indicate that the remaining BCLK periods in the present cycle arenot required. This must happen before the falling (back) edge of BCLK to be recognized inthat BCLK period. /NOWS should be driven low by an open collector or tri-state devicecapable of sinking 20 mA and never be driven high. A slave should not assert /NOWS andCHRDY at the same time./M16If the addressed memory is capable of transferring 16-bits of data at once on the D[15..0] datalines, it may assert /M16, after decoding a valid address. This causes the system board to runa 3-BCLK memory cycle (that is, with only one wait state). /M16 should be driven low by anopen collector or tri-state device capable of sinking 20 mA and never be driven high./IO16If the addressed I/O port is capable of transferring 16-bits of data at once on the D[15..0] datalines, it may assert /IO16, after decoding a valid address. This causes the system board to runa 3-BCLK I/O cycle (that is, with only one wait state). /IO16 should be driven low by anopen collector or tri-state device capable of sinking 20 mA and never be driven high.Bus arbitration signal groupThese signals are used to arbitrate between devices and the system board for control of thebus.DRQ[7..5] and DRQ[3..0]The DRQ (DMA request) lines are used to request a DMA service from the DMA subsystem,or for a 16-bit ISA bus master to request access to the system bus. The request ismade when the DRQ line is driven high and may be asserted asynchronously.The requesting device must hold its DRQ line active until the system board responds byasserting the corresponding /DAK line. For demand mode DMA memory-read I/O-writecycles, DRQx is sampled on the rising edge of BCLK, one BCLK from the end of the presentcycle (the rising edge of /IOWC).For demand mode memory-write I/O-read cycles, DRQx is sampled on the rising edge ofBCLK, 1½ BCLKs from the end of the cycle (the rising edge of /IORC).For 16-bit ISA bus masters, DRQx is sampled on the rising edge of BCLK, two BCLKsbefore the system board asserts DAKx. The trailing edge of DRQx must meet the setup andhold time to the sampling point for proper system operation. The ROM BIOS initializes theDMA controller so that DRQ0 has the highest priority and DRQ7 the lowest. Care must betaken to deactivate the DRQ line without delay, otherwise more than one cycle may begranted. The corresponding /DAK is typically used to reset the DRQ line./DAK[7..5] and /DAK[3..0]The system board asserts a DMA channel’s /DAK (DMA acknowledge) signal low toindicate that the channel has been granted the bus. The DMA device is selected if it finds its/DAK signal, together with either /IORC or /IOWC, asserted. The DMA controller then takescontrol of the bus and proceeds with the DMA cycle. /DAKx is also asserted to acknowledgegranting the bus to a 16-bit ISA bus master. The bus master must then assert /MASTER16 ifit finds its /DAK asserted and proceed with its cycle. Afterwards, the bus master must floatthe address and control lines and make /MASTER16 inactive before the system boarddisasserts the /DAK line.