Data Acquisition

Extended 6-BCLK 16-bit memory accessIf the access and setup times of the 16-bit attached bus memory device are longer than providedfor by the default 3-BCLK bus period, it may, after asserting /M16, assert CHRDY toextend the bus cycle.The system board finds /M16 asserted at the end of T S and begins to run a standard3-BCLK 16-bit memory access. However, at the end of T 2 , it finds CHRDY asserted. Ittherefore runs another wait state (T AW1 in the chart). It expects to find CHRDY disasserted atthe end of this additional wait state but, since it is sampled still active, another wait state isadded. When CHRDY is found inactive (here, at the end of T AW3 ), the bus cycle is completedwith a T C state.Figure 4.9Timing chart of an extended 6-BCLK 16-bit memory access cycle