Data Acquisition

The read or write command signals (/SMRDC, /SMWTC, /MRDC or /MWTC) go active(low) just after the second half of the second machine state, T 2 . This indicates to theexpansion board that it may begin latching the data on the data lines in a write cycle (notethat the write data from the CPU is valid in the first half of T 2 , before the command signalgoes active), or it may begin driving the data lines in a read cycle. The CPU latches the readdata on the trailing edge of the read (/SMRDC, /MRDC) signal, while the adapter-board mustlatch the CPU data on the trailing edge of the write (/SMWTC, /MWTC) signal. This occursat the end of the T S state./M16 is sampled at the end of T S . Since it is inactive (high), an 8-bit, 6-wait state cycle isrun./NOWS is sampled on the trailing edge of BCLK, which is halfway through the wait states,T 2 to T 5 and is acted on if a command signal (a read or write line) is active. Since it is foundinactive (high) in each wait state, the next wait state is inserted by the system board until thedefault number (four) of wait states has been run. If /NOWS is active at any of the samplingpoints, the remaining wait states will be discarded and the T C state is run, completing thecycle.The sampling of CHRDY starts at the end of the last default wait state, T 5 . Since it isinactive (high), no more wait states are added and the cycle is completed with T C.Figure 4.5Timing chart of a standard 6-BCLK 8-bit memory access cycle