Data Acquisition

xiv ContentsC.13 8255-2 mode 1 and 2 timing diagrams 362Appendix D Review of the Intel 8254 timer-counter chip 364D.1 8254 architecture 364Count register (CR) 366Counting element (CE) 366Output latch (OL) 366D.2 8254 registers 366TCCTRL timer/counter control register (offset 3, write only) 366Configuration mode 367Read-back command 368Counter latch command 368TCO - timer/counter 0 (offset 0, read/write) 369TC1 - timer/counter 1 (offset 1, read/write) 369TC2 - timer/counter 2 (offset 2, read/write) 369D.3 Programming a counter 369Data transfer format 370Clock pulse input 370Gate input 370D.4 Read operations 370Simple read operation 371Counter latch command 371Read-back command 371Multiple counter latch 372Counter status information 372Latching both status and current count 373D.5 Counter mode definitions 373Mode 0: interrupt on terminal count 373Mode 1: hardware re-triggerable one-shot 374Mode 2: rate generator 374Mode 3: square wave generator 374Mode 4: software-triggered strobe 375Mode 5: hardware-triggered strobe 375D.6 Interrupt handling 376Appendix E Thermocouple tables 377Type B thermocouple 377Type BP thermocouple 378Type BN thermocouple 378Type E thermocouple 379Type J thermocouples 380Type JP thermocouples 380Type JN thermocouples 381Type K thermocouples 381Type KP thermocouple 382Type KN thermocouple 383