Data Acquisition

Figure 5.26N-bit weighted-current source D/A converterThis method creates an output current, I T, which is the summation of the weighted currentsfrom each of the parallel transistor sources; the current contributed by each transistor set bythe resistances R, 2R, 4R, 8R, etc. The selection of the currents to be summed is determinedby the digital code appearing at the input. For example, if the digital voltage at the MSB islogic low, current will flow through the forward biased diode rather than through the collectorof the transistor, and the transistor will remain off.When the digital voltage at the MSB is logic high, the current flowing through the collectorand emitter of the transistor is equal to V REF /R. A stable reference voltage with suitable temperaturecompensation (base-to-emitter for each transistor) ensures that each transistor producesa constant emitter current inversely proportional to the collector resistance.Since the output from the inverting summing amplifier is V 0 = –I T R/2 the output voltage isdirectly proportional to the voltage reference according to the equationV 0 = V REF (B 0 2 -1 + B 1 2 -2 … + B n-1 2 n-1 )Weighted codes other than straight binary can be converted by proper choice of theweighting resistors.R-2R ladder D/A convertersA D/A converter which uses resistors of only two values, R and 2R, is shown in Figure 5.27.Figure 5.27N-bit R-2R ladder D/A converter