Data Acquisition

• IRQ inputs can be configured as edge-sensitive (normal) or level-sensitive via theinitialization command word (ICW) register4.2.5 Initialization required for InterruptsBefore interrupts can be handled correctly the following functions must be performed:Initialize the ‘interrupt vector table’ located in the first 1024 (1 k) bytes of system memoryto contain the addresses of the interrupt service routines of each of the 256 possibleinterrupts. Each four-byte address consists of an instruction pointer (IP) and code segment(CS) value. A large number of these are initialized by the BIOS and DOS as part of thesystem boot and operating system startup procedures. Initialize the 8259A PIC(s). This islargely initialized by the BIOS as part of the system boot.Enable the system interrupt INTR by setting the interrupt enable flag bit IF in the FLAGSregister.4.2.6 I/O devices requesting interrupt serviceWhen an I/O device asserts an interrupt request, an ordered sequence of events occurs, todirect the CPU to the interrupt service routine (ISR) that will service the specific request.We will assume that any system and remote I/O device initialization that is required toallow the interrupt request to be handled correctly has already occurred.The sequence of events is as follows:• The I/O device hardware activates an interrupt request by asserting its IRQx linefrom ‘low’ to ‘high’. This signal is usually ‘latched’ high by an interrupt requestlatch on the I/O device and remains high until the latch is reset and the interrupt isacknowledged (thus allowing further interrupts). These last tasks are performedby the ISR (see Interrupt service routines, p. 75).• The interrupt controller receives this IRQx interrupt request and prioritizes it withother requests that may be coming in or pending. The interrupt controller willthen send an interrupt request to the CPU on the INTR signal line under thefollowing conditions:− This is the only interrupt request.− A lower priority interrupt is in progress.− Several interrupts are pending but this interrupt has the highest priority.• If the CPU has interrupts enabled, it acknowledges the interrupt request bysending two INTA pulses to the interrupt controller. The first freezes the prioritylevels in the interrupt controller, while the second requests an 8-bit pointer value,called the ‘interrupt type’.• The interrupt controller places the 8-bit interrupt type onto the CPU data bus. This‘interrupt type’ byte is the means by which the CPU knows where to look for theaddress of the interrupt service routine that will service the I/O device.It is used to index the ‘interrupt vector table’ located in the lowest 1024 (1 k)bytes of system memory. Each of the table’s 256 entries (four bytes each)contains the segmented memory addresses of all the ISRs.The CPU multiplies the interrupt type by four (4) to get the offset to theinterrupt vector table where the address of the appropriate ISR will be located.Therefore, for interrupt type S, the address of the initial service routine (ISR) tobe executed will be address 20h (32nd byte).• The CPU saves the information necessary to allow the program currently beingexecuted to resume execution at its next instruction upon completion of the ISR.