Data Acquisition

4.2.8 Sharing interrupts• Upon completion of the ISR all registers saved onto the stack at the start of theISR are retrieved and restored to their original values.• The very last instruction executed within the ISR is the IRET (return frominterrupt) instruction. This signals the CPU that the ISR is complete. Upon executingthis command the CPU retrieves the original CS, IP and FLAGS registervalues from the stack and begins executing the interrupted program at thesegmented memory location CS:IP.At this point the CPU is in exactly the same state as it was when the interruptwas first acknowledged. This allows the program (or possibly a lower priorityinterrupt), which was being executed when the ISR was called, to continue executionunaffected at its next instruction.Restoration of the FLAGS register automatically re-enables interrupts to theCPU.As we have seen an I/O device requesting an interrupt latches its IRQx line high until reset bythe ISR. This precludes more than one I/O device from using the same interrupt line reliablyat the same time.It is possible however for more than one expansion device to use the same interrupt requestline IRQx if each device is guaranteed not to make interrupt requests when another devicemight be using the line. This is achieved by using IRQ line drivers with three state (tri-state)outputs. When an expansion board’s IRQ line is disabled, the output is in a high impedancestate. Pull-up resistors on the system board are used to take the IRQx signal lines to a 5 Vlogic level when not in use.Where I/O devices use the same IRQx line, the interrupt service routine must be able todifferentiate which device is the source of the interrupt.In many I/O interfacing applications and certainly in data acquisition systems, it is oftennecessary to transfer data to or from an interface at data rates higher than those possible usingsimple programmed I/O loops.Microprocessor controlled data transfers within the PC (using the IN(port) and OUT(port)instructions) require a significant amount of CPU time and are performed at a significantlyreduced data rate. Further to this, the CPU cannot perform any other processing duringprogram controlled I/O operations.While the use of interrupts might allow the CPU to perform some concurrent tasks, certainapplications exist where the amount of data to be transferred and the data rate required is toohigh.Two such applications are as follows:• Transferring screen information to the ‘video card adapter’ on board memory• Transferring data from a remote I/O device (data acquisition board) to the PC’smemoryDirect memory access (DMA) facilitates the maximum data transfer rate and microprocessorconcurrence. Unlike programmed or interrupt controlled I/O, where data istransferred via the microprocessor and its internal registers, DMA (as its name implies)transfers data directly between an I/O device and memory (memory to memory DMAtransfers are also possible).