Data Acquisition

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When a counter is configured to enable counting on the active high level of the gate input,the internal counter starts counting the source input transitions at the next active transition,after the gate input pulse goes high and stops counting at the end of the pulse. The duration ofthe gate input pulse (T pw ) is found by reading the count register contents, determining thenumber of known clock transitions that occurred (N), and multiplying this by the timebetween each active transition of the clock (T S ). In this case, it does not matter whether thecount occurs on the positive or negative going edge of the source input. What is moreimportant is the frequency of the known clock signal applied to the source input. As shown inFigure 5.38, an error can occur in the counting of the clock transitions, depending on whenthe pulse begins and ends in relation to the active edge of the clock input. This error can bealmost two full clock cycles. Clearly, the higher the frequency of the clock signal, the smallerthe counting error will be, and the higher the resolution of the pulse measurement. Care mustalso be taken not to choose too high a frequency clocking source input as the counter mayreach its terminal count before the end of the pulse.Figure 5.38Measuring an unknown pulse widthConsider a 500 kHz clock signal, with a clock period of 2 µs, applied to the source input.As a 16-bit counter can count up to 2 16 –1 = 65,535 transitions of the clock input, themaximum measurable pulse width will be 65,535 * 2 µs = 131 ms. Decreasing the frequencyof the clock input source increases the pulse width that can be measured.Selection of the frequency of the clocking source input is therefore a compromise betweenthe resolution and accuracy required of the measurement and the pulse width that must bemeasured.Measuring an unknown frequencyCounters can also be used to measure the frequency of a periodic square wave, irrespective ofits duty cycle. This is accomplished by applying the unknown signal to the source input of thecounter and counting the number of cycles of the signal during a fixed duration pulse appliedto the gate input. The fixed duration gate input signal can come from an external source orfrom the output of another counter, configured to produce a pulse of the required duration.As was the case for pulse width measurement, the counter is configured to enable countingon the active high level of the gate input. The internal counter starts counting the sourceinput transitions at the next active transition after the gate input pulse goes high and stopscounting at the end of the pulse. The frequency of the signal at the source input, (f S ), is foundby determining the number of signal transitions (N), which occurred and dividing this by theperiod of the fixed duration gate input pulse, T pw . f S = N / T pw . This is shown in Figure 5.39.
Figure 5.39Measuring an unknown frequencyThe lower the frequency of the signal that must be measured, the greater should be the fixedduration pulse width to achieve the same resolution and accuracy. If however, the duration ofthe fixed pulse, (T pw ), is too long compared to the clock period, (T S ), of the unknownfrequency signal being measured, the counter may reach its terminal count before the end ofthe pulse. Therefore, the selection of the duration of the fixed pulse at the gate input is acompromise between the resolution and accuracy required and the frequency of the inputsignal being measured.
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Practical Data Acquisition forInstr
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Practical Data Acquisition forInstr
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In less than a decade, the PC has b
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PrefaceContentsxvii1 Introduction 1
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Contents vii4.2.1 Hardware interrup
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Contents ix6.2.3 Functional descrip
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Contents xi9.1 Ethernet and fieldbu
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Contents xiii12.5.2 Pin assignments
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Contents xvType R thermocouple 384T
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A data acquisition and control syst
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FilteringIn noisy environments, it
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are capable of programmed I/O and i
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Plug-in expansion boards are common
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50 mRS-232 Communication InterfaceS
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speeds are of the order of 1 Mbyte/
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14 Practical Data Acquisition for I
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3PC based data acquisition (DAQ) sy
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3.2.3 FilteringIsolation performs s
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The transfer characteristics of a p
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Figure 3.7Ideal band pass filter tr
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Figure 3.11Two-stage Butterworth fi
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As individual signal conditioning m
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ThermocouplesDigitalTransmitterDigi
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Examples of floating signal sources
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espect to the measurement system gr
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Figure 3.26Opto-coupler isolation o
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• Using isolation amplifiers to i
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Figure 3.31Physical representation
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field or if the field is caused by
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Where the shield is grounded (i.e.
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mines the amount of noise in the ci
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For full-duplex systems using balan
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4.1.1 DOSusually consist of a small
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With the advent of Windows as a gra
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UNIX shellSimilar to the DOS comman
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available to the expansion bus. A l
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4.2.7 Interrupt service routinesIt
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Whichever CPU is being used, it mus
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• An I/O device requests a DMA tr
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Normal DMA using on-board FIFOThe D
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ferring samples until the counter r
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The read or write command signals (
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Shortened 3-BCLK 8-bit memory acces
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Extended 6-BCLK 16-bit memory acces
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• A cycle which the expansion boa
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Figure 4.13Timing chart of a shorte
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Figure 4.15Timing chart of an exten
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4.7.2 Expanded memory system (EMS)E
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The IBM PC and early versions of th
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Figure 4.17ISA signal mnemonics, si
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data bus. An example of this happen
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NOWSThe /NOWS (NO wait state) signa
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interrupt lines (1RQ13, 8, 2, 1 and
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one application at a time, it is ne
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The need for PCs to exchange data w
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Figure 4.198-bit 21-line I/O board4
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Address decoding on the 24-line pro
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The write cycle is considered in th
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data acquisition and control system
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Adjustable on-board fixed gain ampl
Page 142 and 143: level applied at the input. When a
Page 144 and 145: Each step effectively divides the r
Page 146 and 147: The operation of a dual slope integ
Page 148 and 149: Code widthThis is the fundamental q
Page 150 and 151: (a) Unipolar offset error(b) Bipola
Page 152 and 153: Changes in temperature result in a
Page 154 and 155: 1 LSB. Therefore, an ideal A/D conv
Page 156 and 157: • The source and level of interru
Page 158 and 159: 5.3.3 Differential inputsTrue diffe
Page 160 and 161: A/D board can divide the input rang
Page 162 and 163: a) DC alias caused by sampling at h
Page 164 and 165: Figure 5.15Frequency spectrum of or
Page 166 and 167: ate be a minimum of about five time
Page 168 and 169: Figure 5.20Many aliases combined wi
Page 170 and 171: initiated. The data is subsequently
Page 172 and 173: Figure 5.22Time skew between channe
Page 174 and 175: For each burst trigger, the A/D boa
Page 176 and 177: Analog output D/A boardsUnlike high
Page 178 and 179: Like the weighted-current source ne
Page 180 and 181: The generation of high frequency si
Page 182 and 183: • The plug-in connector, which pr
Page 184 and 185: Latched digital I/OFor applications
Page 186 and 187: y increasing the resistance of R x
Page 188 and 189: One advantage of this type of relay
Page 190 and 191: Figure 5.36Waveforms showing genera
Page 194 and 195: 6The standardization of the RS-232
Page 196 and 197: A duplex system is designed for sen
Page 198 and 199: Some examples of the HEX and BIN va
Page 200 and 201: In summary, the optional settings f
Page 202 and 203: At the RS-232 receiver the followin
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Page 206 and 207: • Pin 7: Signal ground (common)Th
Page 208 and 209: 6.2.5 Examples of RS-232 interfaces
Page 210 and 211: terminating resistors, approximatel
Page 212 and 213: Another commonly used technique, ba
Page 214 and 215: • Line controlThis applies to hal
Page 216 and 217: The calculation of the block checks
Page 218 and 219: The mechanism of operation of the C
Page 220 and 221: Figure 6.18, has appropriate intern
Page 222 and 223: 77.1 IntroductionAs with other form
Page 224 and 225: inserted in the device. This is its
Page 226 and 227: How frequently logged data is uploa
Page 228 and 229: The following hardware components d
Page 230 and 231: In a typical stand-alone data acqui
Page 232 and 233: The maximum battery life that can b
Page 234 and 235: Input termination resistors, typica
Page 236 and 237: Figure 7.13 shows the standard conn
Page 238 and 239: interface, even at high speed, the
Page 240 and 241: • Use different data formats so t
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Command errors are reported immedia
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• Channel scalingThis automatical
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The channel scan for this type of s
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Data is logged in a fixed non-ASCII
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7.9 Stand-alone logger/controllers
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88.1 IntroductionThe communications
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Figure 8.2GPIB connector (IEEE 488)
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• TalkersA talker is a one-way co
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controller in charge (CIC). The IFC
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Each device connected to the GPIB h
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One of the additional features that
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• The controller temporarily conf
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Table 8.4IEEE 488.2 commandsThe SCP
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Figure 8.9SCPI instrument modelThe
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99.1 Ethernet and fieldbuses for da
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cabling tray etc and the transceive
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transceiver in the MAU and this is
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Advantages of the system include:
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of a cell as well, but these are ig
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Figure 9.8CSMA/CD collisionsAssume
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• PreambleThis field consists of
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of this figure. Some manufacturers
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Grounding has safety and noise conn
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Just as with any technology, each o
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information. The packet is then pla
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There are two types of connectors,
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HOSTClient SoftwareManages Interfac
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Figure 10.6USB connector pinsThere
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The idle states for low- and high-s
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The interrupt transfer type is used
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than in spending a lot of time and
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• The sensitivity of the output/i
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term error (m) in the system and ad
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11.2 Capturing high speed transient
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12IntroductionThe PCMCIA (PCMCIA st
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adapter on a full size computer has
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Pager cards are used in offices and
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Size 85.6 mm × 54.0 mmType I 3.3 m
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The memory only interface is conver
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The AIMS interface supports large d
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12.8 FutureThe card information str
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A/D conversion timeAddressAddress r
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Back-planeBand pass filterBandwidth
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BufferBusBWCache memoryCCDCCIRCCITT
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pixel is subjected to a mathematica
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data between the computer memory an
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FrameFrame grabberFringingFull dupl
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so that they interlock. The PAL sta
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Lux-secondSI unit of light exposure
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NTSCNull modemNumber of channelsNyq
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PortPPIPre-triggerProgram I/OProgra
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whereby the first gray level of eac
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allowing the user to control basic
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input.TrunkUARTUnipolar inputsUnloa
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Appendix BThe information in this s
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Table B.4Controller 2: 16-bit (AT o
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B.5 8253/8254 Counter/timer
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Table B.8Memory map for PC/XT/AT
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Table B.10BIOS data area
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Table B.15ROMTable B.16AT extended
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← ↔ ← ← ← ↔
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Figure B.1Card dimensions for PC/XT
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Appendix CThis section contains bri
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the control register of the 8255. T
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The bits A7 (MSB) down to A0 (LSB)
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Table C.6Instructions for reading o
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The program could also enable the I
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Group AConfiguration Informationto
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C.11 Single-bit set/resetAny of the
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Figure C.15Bi-directional bus (mode
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Figure D.18254 Block diagramFigure
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Figure D.3TCCTRL registerThe functi
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This is the data register of the fi
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• A simple read operation• A co
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The null count bit indicates if the
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For even counts: the output is init
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Appendix EThe IPTS-68 standard defi
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Number of ranges = 2Range #1 -270 t
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Range #2 0 to 1372°COrder of polyn
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Number of Ranges = 4Range #1 -50 to
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Appendix FF.1 IntroductionAll activ
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Table F.3 gives the conversion betw
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The conversion between binary and h
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F.8 Internal representation of info
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12 which is equivalent to: 1100-4 S
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DCDCASDCISDCLDDDIODTDTASDTISENDEOIE
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STBSTRSSWNST(T)TETACSTADSTAGTCATCST
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404 IndexDuplex:full duplex 178half
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406 IndexOpen loop control 285see a
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THIS BOOK WAS DEVELOPED BY IDC TECH
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Data Acquisition

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