Data Acquisition

The timer/counter chip itself consists of a control word register, some logic circuitry, andthe three counters.Each counter consists of a 2-byte wide count register, a 16-bit counting element and a2-byte wide output latch.The count register stores the initial 16-bit count written to a counter. It consists of 2-bytewide registers, which are written to separately. When a counter is programmed with acontrol word, the count register is cleared. Both count register bytes are transferred(loaded) to the counting element simultaneously.The counting element is simply a 16-bit pre-settable synchronous down counter. It cannotbe read from or written to directly. It is automatically loaded on specified conditions fromdata in the count register. The count value is always read from the output latch.The output latch normally follows the counting element. It consists of 2-byte wideregisters, which are read from, separately. If a suitable counter latch command (seebelow) is sent to the counter, the current count value is latched in the output latch until itis read from the counter's data register (TC2, TCI or TC0). Thereafter, the output latchcontinues to follow the counting element.D.2 8254 RegistersAn 8254 occupies four consecutive addresses in the host computer's I/O address space.They are the data registers of timers 0, 1 and 2 and the 8254 control register, shownbelow. Table D.18254 RegistersThe timer/counter control register is used to program, for each counter, the countingmode, the number of bytes to read/write and whether the counter counts in BCD or binaryformat. In addition, this register can be used to perform read-back commands and counterlatch commands. Note that the function and bit names of this register differ according towhether configuration mode, counter latch command, or read-back command is selectedwith bits 7–6 (SC 1 and SC 0 ) and bits 5–4 (RW 1 and RW 0 ).Read-back and counter latch commands, as well as the functions of the differentcounter modes are described below.