Data Acquisition

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Contents xiii12.5.2 Pin assignments 29912.5.3 Memory only cards 29912.5.4 I/O Cards 30012.5.5 I/O with direct memory access 30012.5.6 ATA interface (AT attachment) 30112.5.7 AIMS interface (auto-indexing mass storage) 30212.6 Software 30212.6.1 PC Card environment 30312.7 PC Card enablers and support software 30312.8 Future 30412.8.1 Magazine list and PCMCIA address 30412.8.2 Personal Computer Memory Card International Association 304Appendix A Glossary 305Appendix B IBM PC bus specifications 332B.I Hardware interrupts 332B.2 DMA channels 333B.3 8237 DMA channels 333Refresh (AT) 08F 334B.4 8259 interrupt controller 334B.5 8253 / 8254 counter/timer 336B.6 Bus signal information 344B.7 Card dimensions 346B.8 Centronics interface standard 347Appendix C Review of the Intel 8255 PPI chip 349C.1 DIO0CTRL – control register of the 8255 351C.2 DIOA – port A of the 8255 (offset 0, read/write) 352C.3 DIOB – port B of the 8255 (offset 1, read/write) 353C.4 DIOC – port C of the 8255 (offset 2, read/write) 353C.5 Mode 0: simple I/O 355C.6 Mode 0 programming 355C.7 Mode 1: strobed I/O 355C.8 Mode 1 programming 356C.9 Mode 2: strobed bi-directional bus I/O 358C.10 Mode 2 programming 359C.11 Single-bit set/reset 361C.12 Mixed mode programming 361
xiv ContentsC.13 8255-2 mode 1 and 2 timing diagrams 362Appendix D Review of the Intel 8254 timer-counter chip 364D.1 8254 architecture 364Count register (CR) 366Counting element (CE) 366Output latch (OL) 366D.2 8254 registers 366TCCTRL timer/counter control register (offset 3, write only) 366Configuration mode 367Read-back command 368Counter latch command 368TCO - timer/counter 0 (offset 0, read/write) 369TC1 - timer/counter 1 (offset 1, read/write) 369TC2 - timer/counter 2 (offset 2, read/write) 369D.3 Programming a counter 369<strong>Data</strong> transfer format 370Clock pulse input 370Gate input 370D.4 Read operations 370Simple read operation 371Counter latch command 371Read-back command 371Multiple counter latch 372Counter status information 372Latching both status and current count 373D.5 Counter mode definitions 373Mode 0: interrupt on terminal count 373Mode 1: hardware re-triggerable one-shot 374Mode 2: rate generator 374Mode 3: square wave generator 374Mode 4: software-triggered strobe 375Mode 5: hardware-triggered strobe 375D.6 Interrupt handling 376Appendix E Thermocouple tables 377Type B thermocouple 377Type BP thermocouple 378Type BN thermocouple 378Type E thermocouple 379Type J thermocouples 380Type JP thermocouples 380Type JN thermocouples 381Type K thermocouples 381Type KP thermocouple 382Type KN thermocouple 383
Page 2 and 3: Practical Data Acquisition forInstr
Page 4 and 5: Practical Data Acquisition forInstr
Page 6 and 7: In less than a decade, the PC has b
Page 8 and 9: PrefaceContentsxvii1 Introduction 1
Page 10 and 11: Contents vii4.2.1 Hardware interrup
Page 12 and 13: Contents ix6.2.3 Functional descrip
Page 14 and 15: Contents xi9.1 Ethernet and fieldbu
Page 18 and 19: Contents xvType R thermocouple 384T
Page 20 and 21: A data acquisition and control syst
Page 22 and 23: FilteringIn noisy environments, it
Page 24 and 25: are capable of programmed I/O and i
Page 26 and 27: Plug-in expansion boards are common
Page 28 and 29: 50 mRS-232 Communication InterfaceS
Page 30 and 31: speeds are of the order of 1 Mbyte/
Page 32 and 33: 14 Practical Data Acquisition for I
Page 54 and 55: 3PC based data acquisition (DAQ) sy
Page 56 and 57: 3.2.3 FilteringIsolation performs s
Page 58 and 59: The transfer characteristics of a p
Page 60 and 61: Figure 3.7Ideal band pass filter tr
Page 62 and 63: Figure 3.11Two-stage Butterworth fi
Page 64 and 65: As individual signal conditioning m
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ThermocouplesDigitalTransmitterDigi
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Examples of floating signal sources
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espect to the measurement system gr
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Figure 3.26Opto-coupler isolation o
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• Using isolation amplifiers to i
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Figure 3.31Physical representation
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field or if the field is caused by
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Where the shield is grounded (i.e.
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mines the amount of noise in the ci
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For full-duplex systems using balan
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4.1.1 DOSusually consist of a small
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With the advent of Windows as a gra
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UNIX shellSimilar to the DOS comman
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available to the expansion bus. A l
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4.2.7 Interrupt service routinesIt
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Whichever CPU is being used, it mus
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• An I/O device requests a DMA tr
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Normal DMA using on-board FIFOThe D
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ferring samples until the counter r
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The read or write command signals (
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Shortened 3-BCLK 8-bit memory acces
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Extended 6-BCLK 16-bit memory acces
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• A cycle which the expansion boa
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Figure 4.13Timing chart of a shorte
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Figure 4.15Timing chart of an exten
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4.7.2 Expanded memory system (EMS)E
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The IBM PC and early versions of th
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Figure 4.17ISA signal mnemonics, si
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data bus. An example of this happen
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NOWSThe /NOWS (NO wait state) signa
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interrupt lines (1RQ13, 8, 2, 1 and
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one application at a time, it is ne
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The need for PCs to exchange data w
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Figure 4.198-bit 21-line I/O board4
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Address decoding on the 24-line pro
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The write cycle is considered in th
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data acquisition and control system
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Adjustable on-board fixed gain ampl
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level applied at the input. When a
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Each step effectively divides the r
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The operation of a dual slope integ
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Code widthThis is the fundamental q
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(a) Unipolar offset error(b) Bipola
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Changes in temperature result in a
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1 LSB. Therefore, an ideal A/D conv
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• The source and level of interru
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5.3.3 Differential inputsTrue diffe
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A/D board can divide the input rang
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a) DC alias caused by sampling at h
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Figure 5.15Frequency spectrum of or
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ate be a minimum of about five time
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Figure 5.20Many aliases combined wi
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initiated. The data is subsequently
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Figure 5.22Time skew between channe
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For each burst trigger, the A/D boa
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Analog output D/A boardsUnlike high
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Like the weighted-current source ne
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The generation of high frequency si
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• The plug-in connector, which pr
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Latched digital I/OFor applications
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y increasing the resistance of R x
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One advantage of this type of relay
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Figure 5.36Waveforms showing genera
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When a counter is configured to ena
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6The standardization of the RS-232
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A duplex system is designed for sen
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Some examples of the HEX and BIN va
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In summary, the optional settings f
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At the RS-232 receiver the followin
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110 850300 800600 7001200 5002400 2
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• Pin 7: Signal ground (common)Th
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6.2.5 Examples of RS-232 interfaces
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terminating resistors, approximatel
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Another commonly used technique, ba
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• Line controlThis applies to hal
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The calculation of the block checks
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The mechanism of operation of the C
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Figure 6.18, has appropriate intern
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77.1 IntroductionAs with other form
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inserted in the device. This is its
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How frequently logged data is uploa
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The following hardware components d
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In a typical stand-alone data acqui
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The maximum battery life that can b
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Input termination resistors, typica
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Figure 7.13 shows the standard conn
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interface, even at high speed, the
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• Use different data formats so t
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Command errors are reported immedia
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• Channel scalingThis automatical
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The channel scan for this type of s
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Data is logged in a fixed non-ASCII
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7.9 Stand-alone logger/controllers
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88.1 IntroductionThe communications
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Figure 8.2GPIB connector (IEEE 488)
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• TalkersA talker is a one-way co
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controller in charge (CIC). The IFC
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Each device connected to the GPIB h
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One of the additional features that
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• The controller temporarily conf
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Table 8.4IEEE 488.2 commandsThe SCP
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Figure 8.9SCPI instrument modelThe
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99.1 Ethernet and fieldbuses for da
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cabling tray etc and the transceive
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transceiver in the MAU and this is
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Advantages of the system include:
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of a cell as well, but these are ig
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Figure 9.8CSMA/CD collisionsAssume
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• PreambleThis field consists of
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of this figure. Some manufacturers
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Grounding has safety and noise conn
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Just as with any technology, each o
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information. The packet is then pla
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There are two types of connectors,
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HOSTClient SoftwareManages Interfac
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Figure 10.6USB connector pinsThere
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The idle states for low- and high-s
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The interrupt transfer type is used
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than in spending a lot of time and
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• The sensitivity of the output/i
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term error (m) in the system and ad
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11.2 Capturing high speed transient
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12IntroductionThe PCMCIA (PCMCIA st
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adapter on a full size computer has
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Pager cards are used in offices and
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Size 85.6 mm × 54.0 mmType I 3.3 m
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The memory only interface is conver
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The AIMS interface supports large d
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12.8 FutureThe card information str
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A/D conversion timeAddressAddress r
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Back-planeBand pass filterBandwidth
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BufferBusBWCache memoryCCDCCIRCCITT
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pixel is subjected to a mathematica
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data between the computer memory an
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FrameFrame grabberFringingFull dupl
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so that they interlock. The PAL sta
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Lux-secondSI unit of light exposure
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NTSCNull modemNumber of channelsNyq
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PortPPIPre-triggerProgram I/OProgra
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whereby the first gray level of eac
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allowing the user to control basic
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input.TrunkUARTUnipolar inputsUnloa
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Appendix BThe information in this s
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Table B.4Controller 2: 16-bit (AT o
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B.5 8253/8254 Counter/timer
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Table B.8Memory map for PC/XT/AT
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Table B.10BIOS data area
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Table B.15ROMTable B.16AT extended
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← ↔ ← ← ← ↔
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Figure B.1Card dimensions for PC/XT
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Appendix CThis section contains bri
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the control register of the 8255. T
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The bits A7 (MSB) down to A0 (LSB)
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Table C.6Instructions for reading o
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The program could also enable the I
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Group AConfiguration Informationto
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C.11 Single-bit set/resetAny of the
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Figure C.15Bi-directional bus (mode
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Figure D.18254 Block diagramFigure
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Figure D.3TCCTRL registerThe functi
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This is the data register of the fi
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• A simple read operation• A co
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The null count bit indicates if the
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For even counts: the output is init
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Appendix EThe IPTS-68 standard defi
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Number of ranges = 2Range #1 -270 t
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Range #2 0 to 1372°COrder of polyn
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Number of Ranges = 4Range #1 -50 to
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Appendix FF.1 IntroductionAll activ
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Table F.3 gives the conversion betw
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The conversion between binary and h
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F.8 Internal representation of info
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12 which is equivalent to: 1100-4 S
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DCDCASDCISDCLDDDIODTDTASDTISENDEOIE
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STBSTRSSWNST(T)TETACSTADSTAGTCATCST
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404 IndexDuplex:full duplex 178half
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406 IndexOpen loop control 285see a
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THIS BOOK WAS DEVELOPED BY IDC TECH
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Data Acquisition

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