Data Acquisition

• A cycle shortened by the expansion board to two BCLKs with the /NOWS signal(Figure 4.10)If the expansion board indicates that it is a 16-bit memory device by asserting /M16 (whichis sampled at the beginning of T 2 ), the system board runs a standard 3-BCLK 16-bit memorycycle. The timing is virtually the same as for the standard 8-bit memory cycle. The differencesare: /SBHE is of interest and goes active at the end of T 1 , the read or write commandgoes active just after the beginning of T 2 instead of halfway through T 2 , and now the data istransferred on all 16 of the data lines./NOWS and CHRDY are sampled in the same places as the 8-bit cycle, and as they arefound inactive here, they do not influence the bus cycle.Figure 4.8Timing chart of a standard 3-BCLK 16-bit memory access cycle