Data Acquisition

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(a) Unipolar offset error(b) Bipolar offset errorFigure 5.73-bit A/D converter transfer functions with offset errorsUnipolar and bipolar gain errorsThe gain, or scale, factor is the number which establishes the basic conversion relationshipbetween the analog input values and the digital output codes, e.g. 10 V full-scale. It representsthe straight-line slope of the ideal transfer characteristic. The gain error is defined as thedifference in full-scale values between the ideal and the actual transfer function when any
offset errors are adjusted to zero. It is expressed as a percentage of the nominal full-scalevalue or in LSBs. Gain error affects each code in an equal ratio. Unipolar and bipolar gainerrors are shown in Figure 5.8.(a) Unipolar gain error(b) Bipolar gain errorFigure 5.83-bit A/D converter transfer function with gain errorsOffset and gain driftOffset and gain errors are usually adjustable to zero with calibration, however this calibrationis only valid at the temperature at which it was made.
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Practical Data Acquisition forInstr
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Practical Data Acquisition forInstr
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In less than a decade, the PC has b
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PrefaceContentsxvii1 Introduction 1
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Contents vii4.2.1 Hardware interrup
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Contents ix6.2.3 Functional descrip
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Contents xi9.1 Ethernet and fieldbu
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Contents xiii12.5.2 Pin assignments
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Contents xvType R thermocouple 384T
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A data acquisition and control syst
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FilteringIn noisy environments, it
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are capable of programmed I/O and i
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Plug-in expansion boards are common
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50 mRS-232 Communication InterfaceS
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speeds are of the order of 1 Mbyte/
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14 Practical Data Acquisition for I
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3PC based data acquisition (DAQ) sy
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3.2.3 FilteringIsolation performs s
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The transfer characteristics of a p
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Figure 3.7Ideal band pass filter tr
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Figure 3.11Two-stage Butterworth fi
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As individual signal conditioning m
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ThermocouplesDigitalTransmitterDigi
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Examples of floating signal sources
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espect to the measurement system gr
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Figure 3.26Opto-coupler isolation o
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• Using isolation amplifiers to i
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Figure 3.31Physical representation
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field or if the field is caused by
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Where the shield is grounded (i.e.
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mines the amount of noise in the ci
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For full-duplex systems using balan
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4.1.1 DOSusually consist of a small
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With the advent of Windows as a gra
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UNIX shellSimilar to the DOS comman
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available to the expansion bus. A l
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4.2.7 Interrupt service routinesIt
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Whichever CPU is being used, it mus
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• An I/O device requests a DMA tr
Page 100 and 101: Normal DMA using on-board FIFOThe D
Page 102 and 103: ferring samples until the counter r
Page 104 and 105: The read or write command signals (
Page 106 and 107: Shortened 3-BCLK 8-bit memory acces
Page 108 and 109: Extended 6-BCLK 16-bit memory acces
Page 110 and 111: • A cycle which the expansion boa
Page 112 and 113: Figure 4.13Timing chart of a shorte
Page 114 and 115: Figure 4.15Timing chart of an exten
Page 116 and 117: 4.7.2 Expanded memory system (EMS)E
Page 118 and 119: The IBM PC and early versions of th
Page 120 and 121: Figure 4.17ISA signal mnemonics, si
Page 122 and 123: data bus. An example of this happen
Page 124 and 125: NOWSThe /NOWS (NO wait state) signa
Page 126 and 127: interrupt lines (1RQ13, 8, 2, 1 and
Page 128 and 129: one application at a time, it is ne
Page 130 and 131: The need for PCs to exchange data w
Page 132 and 133: Figure 4.198-bit 21-line I/O board4
Page 134 and 135: Address decoding on the 24-line pro
Page 136 and 137: The write cycle is considered in th
Page 138 and 139: data acquisition and control system
Page 140 and 141: Adjustable on-board fixed gain ampl
Page 142 and 143: level applied at the input. When a
Page 144 and 145: Each step effectively divides the r
Page 146 and 147: The operation of a dual slope integ
Page 148 and 149: Code widthThis is the fundamental q
Page 152 and 153: Changes in temperature result in a
Page 154 and 155: 1 LSB. Therefore, an ideal A/D conv
Page 156 and 157: • The source and level of interru
Page 158 and 159: 5.3.3 Differential inputsTrue diffe
Page 160 and 161: A/D board can divide the input rang
Page 162 and 163: a) DC alias caused by sampling at h
Page 164 and 165: Figure 5.15Frequency spectrum of or
Page 166 and 167: ate be a minimum of about five time
Page 168 and 169: Figure 5.20Many aliases combined wi
Page 170 and 171: initiated. The data is subsequently
Page 172 and 173: Figure 5.22Time skew between channe
Page 174 and 175: For each burst trigger, the A/D boa
Page 176 and 177: Analog output D/A boardsUnlike high
Page 178 and 179: Like the weighted-current source ne
Page 180 and 181: The generation of high frequency si
Page 182 and 183: • The plug-in connector, which pr
Page 184 and 185: Latched digital I/OFor applications
Page 186 and 187: y increasing the resistance of R x
Page 188 and 189: One advantage of this type of relay
Page 190 and 191: Figure 5.36Waveforms showing genera
Page 192 and 193: When a counter is configured to ena
Page 194 and 195: 6The standardization of the RS-232
Page 196 and 197: A duplex system is designed for sen
Page 198 and 199: Some examples of the HEX and BIN va
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In summary, the optional settings f
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At the RS-232 receiver the followin
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110 850300 800600 7001200 5002400 2
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• Pin 7: Signal ground (common)Th
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6.2.5 Examples of RS-232 interfaces
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terminating resistors, approximatel
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Another commonly used technique, ba
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• Line controlThis applies to hal
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The calculation of the block checks
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The mechanism of operation of the C
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Figure 6.18, has appropriate intern
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77.1 IntroductionAs with other form
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inserted in the device. This is its
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How frequently logged data is uploa
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The following hardware components d
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In a typical stand-alone data acqui
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The maximum battery life that can b
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Input termination resistors, typica
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Figure 7.13 shows the standard conn
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interface, even at high speed, the
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• Use different data formats so t
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Command errors are reported immedia
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• Channel scalingThis automatical
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The channel scan for this type of s
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Data is logged in a fixed non-ASCII
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7.9 Stand-alone logger/controllers
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88.1 IntroductionThe communications
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Figure 8.2GPIB connector (IEEE 488)
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• TalkersA talker is a one-way co
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controller in charge (CIC). The IFC
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Each device connected to the GPIB h
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One of the additional features that
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• The controller temporarily conf
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Table 8.4IEEE 488.2 commandsThe SCP
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Figure 8.9SCPI instrument modelThe
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99.1 Ethernet and fieldbuses for da
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cabling tray etc and the transceive
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transceiver in the MAU and this is
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Advantages of the system include:
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of a cell as well, but these are ig
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Figure 9.8CSMA/CD collisionsAssume
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• PreambleThis field consists of
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of this figure. Some manufacturers
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Grounding has safety and noise conn
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Just as with any technology, each o
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information. The packet is then pla
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There are two types of connectors,
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HOSTClient SoftwareManages Interfac
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Figure 10.6USB connector pinsThere
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The idle states for low- and high-s
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The interrupt transfer type is used
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than in spending a lot of time and
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• The sensitivity of the output/i
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term error (m) in the system and ad
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11.2 Capturing high speed transient
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12IntroductionThe PCMCIA (PCMCIA st
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adapter on a full size computer has
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Pager cards are used in offices and
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Size 85.6 mm × 54.0 mmType I 3.3 m
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The memory only interface is conver
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The AIMS interface supports large d
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12.8 FutureThe card information str
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A/D conversion timeAddressAddress r
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Back-planeBand pass filterBandwidth
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BufferBusBWCache memoryCCDCCIRCCITT
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pixel is subjected to a mathematica
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data between the computer memory an
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FrameFrame grabberFringingFull dupl
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so that they interlock. The PAL sta
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Lux-secondSI unit of light exposure
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NTSCNull modemNumber of channelsNyq
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PortPPIPre-triggerProgram I/OProgra
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whereby the first gray level of eac
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allowing the user to control basic
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input.TrunkUARTUnipolar inputsUnloa
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Appendix BThe information in this s
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Table B.4Controller 2: 16-bit (AT o
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B.5 8253/8254 Counter/timer
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Table B.8Memory map for PC/XT/AT
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Table B.10BIOS data area
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Table B.15ROMTable B.16AT extended
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← ↔ ← ← ← ↔
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Figure B.1Card dimensions for PC/XT
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Appendix CThis section contains bri
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the control register of the 8255. T
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The bits A7 (MSB) down to A0 (LSB)
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Table C.6Instructions for reading o
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The program could also enable the I
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Group AConfiguration Informationto
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C.11 Single-bit set/resetAny of the
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Figure C.15Bi-directional bus (mode
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Figure D.18254 Block diagramFigure
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Figure D.3TCCTRL registerThe functi
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This is the data register of the fi
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• A simple read operation• A co
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The null count bit indicates if the
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For even counts: the output is init
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Appendix EThe IPTS-68 standard defi
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Number of ranges = 2Range #1 -270 t
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Range #2 0 to 1372°COrder of polyn
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Number of Ranges = 4Range #1 -50 to
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Appendix FF.1 IntroductionAll activ
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Table F.3 gives the conversion betw
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The conversion between binary and h
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F.8 Internal representation of info
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12 which is equivalent to: 1100-4 S
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DCDCASDCISDCLDDDIODTDTASDTISENDEOIE
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STBSTRSSWNST(T)TETACSTADSTAGTCATCST
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404 IndexDuplex:full duplex 178half
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406 IndexOpen loop control 285see a
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THIS BOOK WAS DEVELOPED BY IDC TECH
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Data Acquisition

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