Data Acquisition

Shortened 3-BCLK 8-bit memory accessThe shortened 8-bit machine cycle is also almost exactly the same as the standard cycle. The/NOWS line is sampled in the middle of the machine states, on the trailing edge of BCLK. InFigure 4.7, the system board finds /NOWS asserted (low) at the middle T 3 , and a commandsignal is active. T 3 would have been a wait state, but because /NOWS is asserted, the systemboard immediately completes the machine cycle by converting it to a T C state. /NOWS maybe asserted anywhere in the bus cycle to indicate that no further wait states are required. If theexpansion board had asserted /NOWS before the middle of T 2 , a 2-BCLK cycle would nothave been generated because in 8-bit cycles, the command signal is not active until after themiddle of T 2 .Figure 4.7Timing chart of a shortened 3-BCLK 8-bit memory access cycleThe next three timing charts show instances of 16-bit memory access:• A standard 3-BCLK cycle (Figure 4.8)• A cycle which the expansion board extends (to six BCLKs) with CHRDY (Figure4.9)