Data Acquisition

During DMA cycles, /MRDC is asserted for read accesses from memory addresses between0h and 00FFFFFFh, regardless of the type of memory responding. This allows the /DAKselected I/O port to receive the data. (The I/O device should not use /MRDC to decode its I/Oaddress.) /MRDC may be driven by expansion boards acting as ISA bus masters./SMRDCThis memory-read signal is derived from /MRDC and has similar timing; the differencebetween the two is that /SMRDC is only active for addresses between 0h and 000FFFFFh(that is, in the first megabyte of memory)./MWTCThis signal is asserted by the system board or ISA bus master to indicate that the addressedmemory slave may latch data from the system data bus. The data is valid at the rising edge ofthe /MWTC signal and maybe latched at this time. During DMA cycles, /MWTC is assertedfor write accesses to memory addresses between 0h and 00FFFFFFh, regardless of the type ofmemory responding. This allows the /DAK selected I/O port to drive the data bus with itsdata. (The I/O device should not use /MWTC to decode its I/O address.) /MWTC may bedriven by expansion boards acting as ISA bus masters./SMWTCThis memory-write signal is derived from /MWTC and has similar timing; the differencebetween the two is that /SMWTC is only active for addresses between 0h and 000FFFFFh(that is, in the first megabyte of memory)./IORCThe I/O-read signal is asserted by the system board or ISA bus master to indicate that theaddressed I/O slave should drive its data onto the system data bus. This should be done after/IORC goes low, and the data must be held valid until after the rising edge of the /IORCsignal to ensure the receiving device obtains valid data. During DMA cycles, the address busdoes not contain an I/O port address; it contains the memory address to which the I/O portdata will be transferred. The I/O port is selected, not by an address decode, but by a /DAKsignal./IOWCThe I/O-write signal is asserted by the system board, or ISA bus master, to indicate that theaddressed I/O slave may latch data from the system data bus. This should be done at therising edge of /IOWC to ensure the receiving device obtains valid data. The system board,DMA device or bus master must drive the data bus before asserting /IOWC. During DMAcycles, the address bus does not contain an I/O port address; it contains the memory addressfrom which the I/O port will latch data. The I/O port is selected, not by an address decode,but by a /DAK signal.CHRDYAn expansion device may use CHRDY (CHannel ReaDY) to lengthen a bus cycle from thedefault time. This allows devices with slow access times also to be attached to the system.The slave drives CHRDY low after decoding a valid address and finding a command signal(any of the six I/O or memory-read or write signals) asserted. This lengthens bus cycles byan integral number of bus cycles. If CHRDY is low, the command signals remain active atleast one BCLK period after it goes inactive. CHRDY should be driven low by an opencollector or tri-state driver and it should never be driven high. It should not be held low formore than 2.5 µs (or about 10 BCLK periods, whichever is less).