Data Acquisition

This limitation is overcome by the insertion of ‘wait states’ into the read or write cycles, a‘wait state’ being the condition where all bus lines remain in their current state for anotherfull bus clock (BCLK) cycle.Upon decoding a valid address and detecting the assertion of one of the control signals(/IORC etc), the I/O device asserts the CHRDY signal low, thus signaling the CPU that a waitstate is required. The CPU will keep inserting wait states for as long as CHRDY is detectedas being low at the falling edge of the BCLK cycle.Where an I/O device does require wait states to be inserted, there should be enoughflexibility to allow easy selection of a variable number of wait states. Most commonly, thenumber of wait states is provided by adjustable hardware settings on the I/O device (switchesor links) with accompanying logic to provide the necessary CHRDY signal. This flexibilityis needed, since the faster the PC to which the I/O device is interfaced, the greater the numberof wait-states that will be required.Note: CHRDY should be driven low by an open collector or tri-state driver and never bedriven high. It should not be held low for more than 2.5 µs or about 10 BCLK periods,whichever is less.Fast I/O devicesAlternatively, an I/O device may be very fast and may not need all the time that is taken in anormal bus cycle.When this is the case, the I/O device must assert the /NOWS (no wait state) signal. Thismust be detected on the falling edge of BCLK for it to be recognized in that BCLK cycle.All the memory and I/O read or write cycles can be shortened, except the 16-bit I/Oread/write cycle.Note: /NOWS should be driven low by an open collector or tri-state driver and never bedriven high.Practical timing considerationsTo determine if our I/O device requires wait states (or in fact if the default number of waitstates may be reduced) the access times of the ICs being addressed on the device must beinvestigated.Referring to the timing diagram of a standard 6 BCLK I/O cycle, we see that the /IORC linegoes low roughly halfway through T 2 . This tells the addressed device to drive the bus datalines D[7..0] with its data.The CPU latches the data present on the bus just before driving the /IORC line high again,which occurs at the end of T 6 .The period over which /IORC is low is about 4.5 machine states which, for a 10 MHzBCLK with a period of 100 ns, corresponds to a period of 450 ns.Taking into account bus delays of 25 ns and allowing a 25 ns setup time for a safe marginof error, then the data must be presented to the data bus 400 ns after /IORC goes low.There are two further considerations:• The access time through the 8255 (access time is the delay between the read linegoing low to valid data on the 8255’s data lines).• The propagation delay through the 74LS245 transceiver of about 25 ns (seemanufacturers’ specification sheets).Looking at the 8255A data sheet (available in the manufacturer’s data book) we see that theread line must be low for 300 ns and the access time is 250 ns (or 200 ns for the faster8255A-5 device).