Data Acquisition

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of this figure. Some manufacturers advise that you can disregard this limit with theirequipment. This can be a risky strategy and should be carefully considered.Table 9.2 Cable segments need not be made from a single homogenous length of cable, and maycomprise of multiple lengths joined by coaxial connectors (two male plugs and aconnector barrel). Although ThickNet (10BASE-5) and ThinNet (10BASE-2) cables havethe same nominal 50 ohm impedance they can only be mixed within the same 10BASE-2cable segment to achieve greater segment length.To achieve maximum performance on 10BASE-5 cable segments, it is preferable thatthe total segment be made from one length of cable or from sections off the same drum ofcable. If multiple sections of cable from different manufacturers are used, then theseshould be standard lengths of 23.4 m, 70.2 m, or 117 m (± 0.5 m), which are odd multiplesof 23.4 m (half wavelength in the cable at 5 MHz). These lengths ensure thatreflections from the cable-to-cable impedance-discontinuities are unlikely to be added inphases. Using these lengths exclusively, a mix of cable sections should be able to makeup the full 500 m segment length.If the cable is from different manufacturers and one suspects potential mismatchproblems, then one should check that signal reflections due to impedance mismatches donot exceed 7% of the incident wave.In 10BASE-5 systems the maximum length, of transceiver cables, is 50 m but it should benoted that this applies to specified IEEE 802.3 compliant cables only. Other AUI cablesusing ribbon or office grade cables can only be used for short distances (less than 12.5 m)so check the manufacturer’s specifications for these!Connection of the transceiver media access units (MAU) to the cable causes signalreflections due to their bridging impedance. Placement of the MAUs must therefore, becontrolled to ensure that reflections from them do not significantly add in phases.In 10BASE-5 systems the MAUs are spaced at 2.5 m multiples, coinciding with thecable markings.In 10BASE-2 systems, the minimum MAU spacing is 0.5 m.The maximum transmission path is made of five segments connected by four repeaters.The total number of segments can be made up of a maximum of three coax segmentscontaining station nodes and two link segments, having no intermediate nodes. This issummarized as the 5-4-3-2 rule.
Table 9.35-4-3-2 ruleIt is important to verify that the above transmission rules are met by all paths betweenany two nodes on the network.Figure 9.10Maximum transmission pathNote that the maximum sized network, of four repeaters, supported by IEEE 802.3, canbe susceptible to timing problems. The maximum configuration is limited by propagationdelay.Note that 10BASE-2 segments should not be used to link 10BASE-5 segments.• 10BASE-5 = 2800 m node to node (5 × 500 m segments + 4repeater cables + 2 AUI)• 10BASE-2 = 925 m node to node (5 × 185 m segments)• 10BASE-T = 100 m node to hubRepeaters are connected to transceivers that count as one node on the segments. Specialtransceivers are used to connect repeaters and these do not implement the signal qualityerror test (SQE).Fiber optic repeaters are available giving up to 3000 m links at 10 Mbps. Check thevendor’s specifications for adherence with IEEE 802.3 repeater-performance andcompliance with the fiber optic inter repeater link (FOIRL) standard.
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Practical Data Acquisition forInstr
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Practical Data Acquisition forInstr
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In less than a decade, the PC has b
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PrefaceContentsxvii1 Introduction 1
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Contents vii4.2.1 Hardware interrup
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Contents ix6.2.3 Functional descrip
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Contents xi9.1 Ethernet and fieldbu
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Contents xiii12.5.2 Pin assignments
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Contents xvType R thermocouple 384T
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A data acquisition and control syst
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FilteringIn noisy environments, it
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are capable of programmed I/O and i
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Plug-in expansion boards are common
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50 mRS-232 Communication InterfaceS
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speeds are of the order of 1 Mbyte/
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14 Practical Data Acquisition for I
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3PC based data acquisition (DAQ) sy
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3.2.3 FilteringIsolation performs s
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The transfer characteristics of a p
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Figure 3.7Ideal band pass filter tr
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Figure 3.11Two-stage Butterworth fi
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As individual signal conditioning m
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ThermocouplesDigitalTransmitterDigi
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Examples of floating signal sources
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espect to the measurement system gr
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Figure 3.26Opto-coupler isolation o
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• Using isolation amplifiers to i
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Figure 3.31Physical representation
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field or if the field is caused by
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Where the shield is grounded (i.e.
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mines the amount of noise in the ci
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For full-duplex systems using balan
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4.1.1 DOSusually consist of a small
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With the advent of Windows as a gra
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UNIX shellSimilar to the DOS comman
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available to the expansion bus. A l
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4.2.7 Interrupt service routinesIt
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Whichever CPU is being used, it mus
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• An I/O device requests a DMA tr
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Normal DMA using on-board FIFOThe D
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ferring samples until the counter r
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The read or write command signals (
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Shortened 3-BCLK 8-bit memory acces
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Extended 6-BCLK 16-bit memory acces
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• A cycle which the expansion boa
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Figure 4.13Timing chart of a shorte
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Figure 4.15Timing chart of an exten
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4.7.2 Expanded memory system (EMS)E
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The IBM PC and early versions of th
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Figure 4.17ISA signal mnemonics, si
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data bus. An example of this happen
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NOWSThe /NOWS (NO wait state) signa
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interrupt lines (1RQ13, 8, 2, 1 and
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one application at a time, it is ne
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The need for PCs to exchange data w
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Figure 4.198-bit 21-line I/O board4
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Address decoding on the 24-line pro
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The write cycle is considered in th
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data acquisition and control system
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Adjustable on-board fixed gain ampl
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level applied at the input. When a
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Each step effectively divides the r
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The operation of a dual slope integ
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Code widthThis is the fundamental q
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(a) Unipolar offset error(b) Bipola
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Changes in temperature result in a
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1 LSB. Therefore, an ideal A/D conv
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• The source and level of interru
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5.3.3 Differential inputsTrue diffe
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A/D board can divide the input rang
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a) DC alias caused by sampling at h
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Figure 5.15Frequency spectrum of or
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ate be a minimum of about five time
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Figure 5.20Many aliases combined wi
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initiated. The data is subsequently
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Figure 5.22Time skew between channe
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For each burst trigger, the A/D boa
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Analog output D/A boardsUnlike high
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Like the weighted-current source ne
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The generation of high frequency si
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• The plug-in connector, which pr
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Latched digital I/OFor applications
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y increasing the resistance of R x
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One advantage of this type of relay
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Figure 5.36Waveforms showing genera
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When a counter is configured to ena
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6The standardization of the RS-232
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A duplex system is designed for sen
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Some examples of the HEX and BIN va
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In summary, the optional settings f
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At the RS-232 receiver the followin
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110 850300 800600 7001200 5002400 2
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• Pin 7: Signal ground (common)Th
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6.2.5 Examples of RS-232 interfaces
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terminating resistors, approximatel
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Another commonly used technique, ba
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• Line controlThis applies to hal
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The calculation of the block checks
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The mechanism of operation of the C
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Figure 6.18, has appropriate intern
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77.1 IntroductionAs with other form
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inserted in the device. This is its
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How frequently logged data is uploa
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The following hardware components d
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In a typical stand-alone data acqui
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The maximum battery life that can b
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Page 236 and 237: Figure 7.13 shows the standard conn
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Page 240 and 241: • Use different data formats so t
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Page 244 and 245: • Channel scalingThis automatical
Page 246 and 247: The channel scan for this type of s
Page 248 and 249: Data is logged in a fixed non-ASCII
Page 250 and 251: 7.9 Stand-alone logger/controllers
Page 252 and 253: 88.1 IntroductionThe communications
Page 254 and 255: Figure 8.2GPIB connector (IEEE 488)
Page 256 and 257: • TalkersA talker is a one-way co
Page 258 and 259: controller in charge (CIC). The IFC
Page 260 and 261: Each device connected to the GPIB h
Page 262 and 263: One of the additional features that
Page 264 and 265: • The controller temporarily conf
Page 266 and 267: Table 8.4IEEE 488.2 commandsThe SCP
Page 268 and 269: Figure 8.9SCPI instrument modelThe
Page 270 and 271: 99.1 Ethernet and fieldbuses for da
Page 272 and 273: cabling tray etc and the transceive
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Page 276 and 277: Advantages of the system include:
Page 278 and 279: of a cell as well, but these are ig
Page 280 and 281: Figure 9.8CSMA/CD collisionsAssume
Page 282 and 283: • PreambleThis field consists of
Page 286 and 287: Grounding has safety and noise conn
Page 288 and 289: Just as with any technology, each o
Page 290 and 291: information. The packet is then pla
Page 292 and 293: There are two types of connectors,
Page 294 and 295: HOSTClient SoftwareManages Interfac
Page 296 and 297: Figure 10.6USB connector pinsThere
Page 298 and 299: The idle states for low- and high-s
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Page 304 and 305: • The sensitivity of the output/i
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Page 308 and 309: 11.2 Capturing high speed transient
Page 310 and 311: 12IntroductionThe PCMCIA (PCMCIA st
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Page 316 and 317: Size 85.6 mm × 54.0 mmType I 3.3 m
Page 318 and 319: The memory only interface is conver
Page 320 and 321: The AIMS interface supports large d
Page 322 and 323: 12.8 FutureThe card information str
Page 324 and 325: A/D conversion timeAddressAddress r
Page 326 and 327: Back-planeBand pass filterBandwidth
Page 328 and 329: BufferBusBWCache memoryCCDCCIRCCITT
Page 330 and 331: pixel is subjected to a mathematica
Page 332 and 333: data between the computer memory an
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FrameFrame grabberFringingFull dupl
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so that they interlock. The PAL sta
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Lux-secondSI unit of light exposure
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NTSCNull modemNumber of channelsNyq
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PortPPIPre-triggerProgram I/OProgra
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whereby the first gray level of eac
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allowing the user to control basic
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input.TrunkUARTUnipolar inputsUnloa
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Appendix BThe information in this s
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Table B.4Controller 2: 16-bit (AT o
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B.5 8253/8254 Counter/timer
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Table B.8Memory map for PC/XT/AT
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Table B.10BIOS data area
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Table B.15ROMTable B.16AT extended
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← ↔ ← ← ← ↔
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Figure B.1Card dimensions for PC/XT
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Appendix CThis section contains bri
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the control register of the 8255. T
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The bits A7 (MSB) down to A0 (LSB)
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Table C.6Instructions for reading o
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The program could also enable the I
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Group AConfiguration Informationto
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C.11 Single-bit set/resetAny of the
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Figure C.15Bi-directional bus (mode
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Figure D.18254 Block diagramFigure
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Figure D.3TCCTRL registerThe functi
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This is the data register of the fi
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• A simple read operation• A co
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The null count bit indicates if the
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For even counts: the output is init
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Appendix EThe IPTS-68 standard defi
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Number of ranges = 2Range #1 -270 t
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Range #2 0 to 1372°COrder of polyn
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Number of Ranges = 4Range #1 -50 to
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Appendix FF.1 IntroductionAll activ
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Table F.3 gives the conversion betw
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The conversion between binary and h
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F.8 Internal representation of info
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12 which is equivalent to: 1100-4 S
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DCDCASDCISDCLDDDIODTDTASDTISENDEOIE
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STBSTRSSWNST(T)TETACSTADSTAGTCATCST
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404 IndexDuplex:full duplex 178half
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406 IndexOpen loop control 285see a
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THIS BOOK WAS DEVELOPED BY IDC TECH
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