Data Acquisition

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terminating resistors, approximately two times the characteristic impedance (Z o ) of the line,are fitted at the extreme ends. These resistors are typically between 100 and 500 Ω andreduce the effect of reflections at the ends of the line. For twisted pairs, the characteristicimpedance is typically between 100 to 120 Ω.During operation, there maybe periods of time when all RS-485 line drivers are off and thecommunications lines are in ‘idle’. In this condition, the lines are susceptible to noise pickup,which can be interpreted as random characters on the communications line. A solution to thisproblem is to incorporate 1 kΩ bias resistors as indicated in the terminated multidrop networkof Figure 6.8. These resistors will maintain the data lines in a mark condition when thesystem is ‘idle’.Figure 6.8RS-485 multidrop networks6.3.1 RS-485 repeatersRS-485 line drivers are designed to drive up to 32 receivers on a network. This limitation canbe overcome by employing an RS-485 repeater. The repeater is a two-port device that retransmitsdata received on one side, at full voltage levels, to the network on the other side.Consequently, another 31 devices may be connected for each repeater used, as shown inFigure 6.9.
Figure 6.9RS-485 multidrop networksThe main features of the four most common EIA interface standards are compared below: Mode of operation Unbalanced DifferentialMax no. of drivers & receivers online1 Driver1 Receiver32 Drivers32 ReceiversMaximum cable length 15 m 1,200 mMaximum data rate 20 kbps 10 MbpsMaximum common mode voltage 25 V +12 V to –7 VDriver output signal± 5.0 V min ± 1.5 V min± 25 V max ± 6.0 V maxDriver load >3 kΩ 60 ΩDriver outputresistance(high-Z state)Power ‘On’Power ‘Off’n/a300 Ω100 microA–7V≤Vcm ≤12V100 microA–7V≤Vcm ≤12VReceiver input resistance 3 kΩ to 7 kΩ >12 kΩReceiver sensitivity ±3.0 V ± 200 mV–2V≤Vcm ≤12VTable 6.6Comparisons of main features of EIA-232 and EIA-485
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Practical Data Acquisition forInstr
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Practical Data Acquisition forInstr
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In less than a decade, the PC has b
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PrefaceContentsxvii1 Introduction 1
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Contents vii4.2.1 Hardware interrup
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Contents ix6.2.3 Functional descrip
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Contents xi9.1 Ethernet and fieldbu
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Contents xiii12.5.2 Pin assignments
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Contents xvType R thermocouple 384T
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A data acquisition and control syst
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FilteringIn noisy environments, it
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are capable of programmed I/O and i
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Plug-in expansion boards are common
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50 mRS-232 Communication InterfaceS
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speeds are of the order of 1 Mbyte/
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14 Practical Data Acquisition for I
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3PC based data acquisition (DAQ) sy
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3.2.3 FilteringIsolation performs s
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The transfer characteristics of a p
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Figure 3.7Ideal band pass filter tr
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Figure 3.11Two-stage Butterworth fi
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As individual signal conditioning m
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ThermocouplesDigitalTransmitterDigi
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Examples of floating signal sources
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espect to the measurement system gr
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Figure 3.26Opto-coupler isolation o
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• Using isolation amplifiers to i
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Figure 3.31Physical representation
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field or if the field is caused by
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Where the shield is grounded (i.e.
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mines the amount of noise in the ci
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For full-duplex systems using balan
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4.1.1 DOSusually consist of a small
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With the advent of Windows as a gra
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UNIX shellSimilar to the DOS comman
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available to the expansion bus. A l
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4.2.7 Interrupt service routinesIt
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Whichever CPU is being used, it mus
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• An I/O device requests a DMA tr
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Normal DMA using on-board FIFOThe D
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ferring samples until the counter r
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The read or write command signals (
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Shortened 3-BCLK 8-bit memory acces
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Extended 6-BCLK 16-bit memory acces
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• A cycle which the expansion boa
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Figure 4.13Timing chart of a shorte
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Figure 4.15Timing chart of an exten
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4.7.2 Expanded memory system (EMS)E
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The IBM PC and early versions of th
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Figure 4.17ISA signal mnemonics, si
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data bus. An example of this happen
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NOWSThe /NOWS (NO wait state) signa
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interrupt lines (1RQ13, 8, 2, 1 and
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one application at a time, it is ne
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The need for PCs to exchange data w
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Figure 4.198-bit 21-line I/O board4
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Address decoding on the 24-line pro
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The write cycle is considered in th
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data acquisition and control system
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Adjustable on-board fixed gain ampl
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level applied at the input. When a
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Each step effectively divides the r
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The operation of a dual slope integ
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Code widthThis is the fundamental q
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(a) Unipolar offset error(b) Bipola
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Changes in temperature result in a
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1 LSB. Therefore, an ideal A/D conv
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• The source and level of interru
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5.3.3 Differential inputsTrue diffe
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Page 164 and 165: Figure 5.15Frequency spectrum of or
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Page 168 and 169: Figure 5.20Many aliases combined wi
Page 170 and 171: initiated. The data is subsequently
Page 172 and 173: Figure 5.22Time skew between channe
Page 174 and 175: For each burst trigger, the A/D boa
Page 176 and 177: Analog output D/A boardsUnlike high
Page 178 and 179: Like the weighted-current source ne
Page 180 and 181: The generation of high frequency si
Page 182 and 183: • The plug-in connector, which pr
Page 184 and 185: Latched digital I/OFor applications
Page 186 and 187: y increasing the resistance of R x
Page 188 and 189: One advantage of this type of relay
Page 190 and 191: Figure 5.36Waveforms showing genera
Page 192 and 193: When a counter is configured to ena
Page 194 and 195: 6The standardization of the RS-232
Page 196 and 197: A duplex system is designed for sen
Page 198 and 199: Some examples of the HEX and BIN va
Page 200 and 201: In summary, the optional settings f
Page 202 and 203: At the RS-232 receiver the followin
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Page 206 and 207: • Pin 7: Signal ground (common)Th
Page 208 and 209: 6.2.5 Examples of RS-232 interfaces
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Page 214 and 215: • Line controlThis applies to hal
Page 216 and 217: The calculation of the block checks
Page 218 and 219: The mechanism of operation of the C
Page 220 and 221: Figure 6.18, has appropriate intern
Page 222 and 223: 77.1 IntroductionAs with other form
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Page 226 and 227: How frequently logged data is uploa
Page 228 and 229: The following hardware components d
Page 230 and 231: In a typical stand-alone data acqui
Page 232 and 233: The maximum battery life that can b
Page 234 and 235: Input termination resistors, typica
Page 236 and 237: Figure 7.13 shows the standard conn
Page 238 and 239: interface, even at high speed, the
Page 240 and 241: • Use different data formats so t
Page 242 and 243: Command errors are reported immedia
Page 244 and 245: • Channel scalingThis automatical
Page 246 and 247: The channel scan for this type of s
Page 248 and 249: Data is logged in a fixed non-ASCII
Page 250 and 251: 7.9 Stand-alone logger/controllers
Page 252 and 253: 88.1 IntroductionThe communications
Page 254 and 255: Figure 8.2GPIB connector (IEEE 488)
Page 256 and 257: • TalkersA talker is a one-way co
Page 258 and 259: controller in charge (CIC). The IFC
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Each device connected to the GPIB h
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One of the additional features that
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• The controller temporarily conf
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Table 8.4IEEE 488.2 commandsThe SCP
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Figure 8.9SCPI instrument modelThe
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99.1 Ethernet and fieldbuses for da
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cabling tray etc and the transceive
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transceiver in the MAU and this is
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Advantages of the system include:
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of a cell as well, but these are ig
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Figure 9.8CSMA/CD collisionsAssume
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• PreambleThis field consists of
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of this figure. Some manufacturers
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Grounding has safety and noise conn
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Just as with any technology, each o
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information. The packet is then pla
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There are two types of connectors,
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HOSTClient SoftwareManages Interfac
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Figure 10.6USB connector pinsThere
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The idle states for low- and high-s
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The interrupt transfer type is used
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than in spending a lot of time and
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• The sensitivity of the output/i
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term error (m) in the system and ad
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11.2 Capturing high speed transient
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12IntroductionThe PCMCIA (PCMCIA st
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adapter on a full size computer has
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Pager cards are used in offices and
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Size 85.6 mm × 54.0 mmType I 3.3 m
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The memory only interface is conver
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The AIMS interface supports large d
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12.8 FutureThe card information str
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A/D conversion timeAddressAddress r
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Back-planeBand pass filterBandwidth
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BufferBusBWCache memoryCCDCCIRCCITT
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pixel is subjected to a mathematica
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data between the computer memory an
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FrameFrame grabberFringingFull dupl
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so that they interlock. The PAL sta
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Lux-secondSI unit of light exposure
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NTSCNull modemNumber of channelsNyq
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PortPPIPre-triggerProgram I/OProgra
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whereby the first gray level of eac
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allowing the user to control basic
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input.TrunkUARTUnipolar inputsUnloa
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Appendix BThe information in this s
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Table B.4Controller 2: 16-bit (AT o
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B.5 8253/8254 Counter/timer
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Table B.8Memory map for PC/XT/AT
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Table B.10BIOS data area
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Table B.15ROMTable B.16AT extended
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← ↔ ← ← ← ↔
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Figure B.1Card dimensions for PC/XT
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Appendix CThis section contains bri
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the control register of the 8255. T
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The bits A7 (MSB) down to A0 (LSB)
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Table C.6Instructions for reading o
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The program could also enable the I
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Group AConfiguration Informationto
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C.11 Single-bit set/resetAny of the
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Figure C.15Bi-directional bus (mode
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Figure D.18254 Block diagramFigure
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Figure D.3TCCTRL registerThe functi
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This is the data register of the fi
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• A simple read operation• A co
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The null count bit indicates if the
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For even counts: the output is init
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Appendix EThe IPTS-68 standard defi
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Number of ranges = 2Range #1 -270 t
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Range #2 0 to 1372°COrder of polyn
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Number of Ranges = 4Range #1 -50 to
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Appendix FF.1 IntroductionAll activ
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Table F.3 gives the conversion betw
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The conversion between binary and h
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F.8 Internal representation of info
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12 which is equivalent to: 1100-4 S
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DCDCASDCISDCLDDDIODTDTASDTISENDEOIE
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STBSTRSSWNST(T)TETACSTADSTAGTCATCST
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404 IndexDuplex:full duplex 178half
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406 IndexOpen loop control 285see a
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THIS BOOK WAS DEVELOPED BY IDC TECH
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