Data Acquisition

available to the expansion bus. A list of standard and common interrupt allocations isprovided in Table 4.1 below.Table 4.1InterruptlevelInterrupt typenumberStandard deviceAvailable onISA busIRQ0 8 (8h) System timer NoIRQ1 9 (9h) Keyboard NoIRQ2 10 (Ah) Redirected to IRQ9 Same as IRQ9IRQ8 112 (70h) Real time clock NoIRQ9 113 (71h) Display adapter (VGA)network cardYesIRQ10 114 (72h) Free YesIRQ11 115 (73h) Free YesIRQ12 116 (74h) Free YesIRQ13 117 (75h) Math coprocessor NoIRQ14 118 (76h) Hard drive controller YesIRQ15 119 (77h) Free YesIRQ3 11 (Bh) Serial port 2 (and / or 4) YesIRQ4 12 (Ch) Serial port 1 (and / or 3) YesIRQ5 13 (Dh) Parallel port 2 YesIRQ6 14 (Eh) Floppy drive controller YesIRQ7 15 (Fh) Parallel port 1 YesThe 8259A PIC has the following features:• IRQ inputs are prioritized with the lower numbered inputs having the higherpriority. When the slave PIC is cascaded into IRQ2 of the master PIC on thePC/AT type systems, IRQ0 and IRQ1 have a higher priority than the slave PICIRQs (IRQS–IRQ15). However IRQ3–IRQ7 have a lower priority than the slavePICs IRQ8–IRQ15• Since IRQ2 is not available for expansion boards, any interrupt requests on IRQ2(from expansion boards originally designed for use in XT type boards) aretransparently routed to IRQ9 by the system board• IRQs can be individually masked (enabled or disabled). This is performed bywriting to the PIC’s operation command register (OCWl) – a single bytedescribing the interrupt status for the eight IRQ inputs• It automatically issues the interrupt type bytes to the CPU during the INTA cycles(see I/O devices requesting interrupt service p. 74). The master PIC can generateinterrupt types 08h to 00h, whilst the slave PIC (when available) is programmedto generate interrupt types 70h to 77h, see Table 4.1• It automatically tracks which interrupts are being serviced by the CPU, to preventmultiple occurrences of the same interrupt