Data Acquisition

For even counts: the output is initially high. On the next clock pulse, the initial count isloaded. On subsequent clock pulses, it is decremented by two. When the count expires,the output toggles, and the counter is reloaded with the initial count. This process isrepeated indefinitely.For odd counts: the output is initially high. On the next clock pulse, the initial countminus one (an even number) is loaded. On subsequent clock pulses, it is decremented bytwo. One clock pulse after the count expires, the output goes low, and the counter isreloaded with the initial count minus one. Subsequent clock pulses continue to decrementthe count by two. When the count expires, the output goes high again and the counter isreloaded with the initial count minus one. This process is repeated indefinitely. So for oddcounts, the output is high for (N+1)/2 counts and low for (N–1)/2 counts, or high for onecount longer than it is low.Mode 3 is typically used to generate an output frequency.After the mode byte is written to the control register, the output is high. Once an initialcount has been written, the output remains high until the counter has counted down tozero. The output then goes low for one clock pulse and then goes high again. Thecounting sequence is triggered by writing an initial count.The gate input inhibits counting when low, and enables counting when high. It has noeffect on the output.After the control word and initial count have been written, the counter is loaded on thenext clock pulse. This clock pulse does not decrement the count, so for an initial count ofN, the output strobes low N+1 clock pulses after the initial count was written.If a new count is written while counting, it will be loaded on the next clock pulse andcounting will continue from the new count. If a two-byte count is written, the first bytewritten has no effect on counting. After the second byte is written, the full count is loadedon the next clock pulse. This allows the counting sequence to be re-triggered by software.Again the output strobes low after N+1 clock pulses.Using the internal oscillator or bus clock, this mode can be used to generate a negativepulse on the external output after a programmable time. With an external clock source, itgenerates a pulse after a programmable number of events. This mode is similar to mode 4 except that the counting is triggered by a rising edge onthe counter’s gate input.After the control word and initial count have been written, the output is high. Thecounter is loaded on the next clock pulse after a trigger is received. This clock pulse doesnot decrement the count. The output remains high until the counter has counted down tozero. The output goes low for one clock pulse and then goes high again. Therefore, for aninitial count of N, the output strobes low N+1 clock pulses after the initial count waswritten.The counting sequence is re-triggerable: a trigger causes the counter to be loaded withthe initial count on the next clock pulse. The output will not strobe low until N+1 clockpulses after any trigger. The gate input has no effect on the output.If a new count is written while counting, it will have no effect on the current countsequence. If a trigger is received after the new count is written but before the currentcount expires, the counter will be reloaded on the next clock pulse and counting willcontinue from there.